33.4 Maximum Clock Frequencies

Table 33-3. Maximum GCLK Generator Output Frequencies
SymbolDescriptionConditionsMax.Units
fGCLKGEN0 / fGCLK_MAIN

fGCLKGEN1

fGCLKGEN2

fGCLKGEN3

fGCLKGEN4

fGCLKGEN5

fGCLKGEN6

fGCLKGEN7

GCLK Generator Output FrequencyUndivided


48
Divided32MHz
Table 33-4. Maximum Peripheral Clock Frequencies
SymbolDescriptionMax.Units
fCPUCPU clock frequency32MHz
fAHBAHB clock frequency32MHz
fAPBAAPBA clock frequency32MHz
fAPBBAPBB clock frequency32MHz
fAPBCAPBC clock frequency32MHz
fGCLK_DFLL48M_REFDFLL48M Reference clock frequency35.1kHz
fGCLK_WDTWDT input clock frequency48MHz
fGCLK_RTCRTC input clock frequency48MHz
fGCLK_EICEIC input clock frequency48MHz
fGCLK_EVSYS_CHANNEL_0EVSYS channel 0 input clock frequency48MHz
fGCLK_EVSYS_CHANNEL_1EVSYS channel 1 input clock frequency48MHz
fGCLK_EVSYS_CHANNEL_2EVSYS channel 2 input clock frequency48MHz
fGCLK_EVSYS_CHANNEL_3EVSYS channel 3 input clock frequency48MHz
fGCLK_EVSYS_CHANNEL_4EVSYS channel 4 input clock frequency48MHz
fGCLK_EVSYS_CHANNEL_5EVSYS channel 5 input clock frequency48MHz
fGCLK_EVSYS_CHANNEL_6EVSYS channel 6 input clock frequency48MHz
fGCLK_EVSYS_CHANNEL_7EVSYS channel 7 input clock frequency48MHz
fGCLK_SERCOMx_SLOWCommon SERCOM slow input clock frequency48MHz
fGCLK_SERCOM0_CORESERCOM0 input clock frequency48MHz
fGCLK_SERCOM1_CORESERCOM1 input clock frequency48MHz
fGCLK_SERCOM2_CORESERCOM2 input clock frequency48MHz
fGCLK_SERCOM3_CORESERCOM3 input clock frequency48MHz
fGCLK_SERCOM4_CORESERCOM4 input clock frequency48MHz
fGCLK_SERCOM5_CORESERCOM5 input clock frequency48MHz
fGCLK_TC0, GCLK_TC1TC0,TC1 input clock frequency48MHz
fGCLK_TC2, GCLK_TC3TC2,TC3 input clock frequency48MHz
fGCLK_TC4, GCLK_TC5TC4,TC5 input clock frequency48MHz
fGCLK_TC6, GCLK_TC7TC6,TC7 input clock frequency48MHz
fGCLK_ADCADC input clock frequency48MHz
fGCLK_AC_DIGAC digital input clock frequency48MHz
fGCLK_AC_ANAAC analog input clock frequency64kHz
fGCLK_DACDAC input clock frequency48MHz
fGCLK_PTCPTC input clock frequency48MHz