16.15 Register Summary - I/O Ports
| Offset | Name | Bit Pos. | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|
0x00 ... 0x0B | Reserved | |||||||||
| 0x0C | PORTA | 7:0 | RA5 | RA4 | RA3 | RA2 | RA1 | RA0 | ||
0x0D | Reserved | |||||||||
| 0x0E | PORTC | 7:0 | RC5 | RC4 | RC3 | RC2 | RC1 | RC0 | ||
0x0F ... 0x11 | Reserved | |||||||||
| 0x12 | TRISA | 7:0 | TRISA5 | TRISA4 | Reserved | TRISA2 | TRISA1 | TRISA0 | ||
0x13 | Reserved | |||||||||
| 0x14 | TRISC | 7:0 | TRISC5 | TRISC4 | TRISC3 | TRISC2 | TRISC1 | TRISC0 | ||
0x15 ... 0x17 | Reserved | |||||||||
| 0x18 | LATA | 7:0 | LATA5 | LATA4 | LATA2 | LATA1 | LATA0 | |||
0x19 | Reserved | |||||||||
| 0x1A | LATC | 7:0 | LATC5 | LATC4 | LATC3 | LATC2 | LATC1 | LATC0 | ||
0x1B ... 0x1E8B | Reserved | |||||||||
| 0x1E8C | ANSELA | 7:0 | ANSELA5 | ANSELA4 | ANSELA2 | ANSELA1 | ANSELA0 | |||
| 0x1E8D | WPUA | 7:0 | WPUA5 | WPUA4 | WPUA3 | WPUA2 | WPUA1 | WPUA0 | ||
| 0x1E8E | ODCONA | 7:0 | ODCA5 | ODCA4 | ODCA2 | ODCA1 | ODCA0 | |||
| 0x1E8F | SLRCONA | 7:0 | SLRA5 | SLRA4 | SLRA2 | SLRA1 | SLRA0 | |||
| 0x1E90 | INLVLA | 7:0 | INLVLA5 | INLVLA4 | INLVLA3 | INLVLA2 | INLVLA1 | INLVLA0 | ||
0x1E91 ... 0x1E9F | Reserved | |||||||||
| 0x1EA0 | ANSELC | 7:0 | ANSELC5 | ANSELC4 | ANSELC3 | ANSELC2 | ANSELC1 | ANSELC0 | ||
| 0x1EA1 | WPUC | 7:0 | WPUC5 | WPUC4 | WPUC3 | WPUC2 | WPUC1 | WPUC0 | ||
| 0x1EA2 | ODCONC | 7:0 | ODCC5 | ODCC4 | ODCC3 | ODCC2 | ODCC1 | ODCC0 | ||
| 0x1EA3 | SLRCONC | 7:0 | SLRC5 | SLRC4 | SLRC3 | SLRC2 | SLRC1 | SLRC0 | ||
| 0x1EA4 | INLVLC | 7:0 | INLVLC5 | INLVLC4 | INLVLC3 | INLVLC2 | INLVLC1 | INLVLC0 | ||
0x1EA5 ... 0x1EE0 | Reserved | |||||||||
| 0x1EE1 | RA1I2C | 7:0 | SLEW | PU[1:0] | TH[1:0] | |||||
| 0x1EE2 | RA2I2C | 7:0 | SLEW | PU[1:0] | TH[1:0] | |||||
0x1EE3 ... 0x1EE8 | Reserved | |||||||||
| 0x1EE9 | RC0I2C | 7:0 | SLEW | PU[1:0] | TH[1:0] | |||||
| 0x1EEA | RC1I2C | 7:0 | SLEW | PU[1:0] | TH[1:0] | |||||