12.10.9 PIR2

Peripheral Interrupt Request Register 2

Note: Interrupt flag bits are set when an Interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable (GIE) bit. User software may ensure the appropriate interrupt flag bits are cleared before enabling an interrupt.

Name:	PIR2
Offset:	0x008E


Bit	7	6	5	4	3	2	1	0
	CLC2IF	CLC1IF		NCO1IF	CCP2IF	CCP1IF	TMR6IF	TMR4IF
Access	R/W/HS	R/W/HS		R/W/HS	R/W/HS	R/W/HS	R/W/HS	R/W/HS
Reset	0	0		0	0	0	0	0

Bit 7 – CLC2IF CLC2 Interrupt Flag

Value	Description
1	CLC2 interrupt has occurred (must be cleared in software)
0	CLC2 interrupt event has not occurred

Bit 6 – CLC1IF CLC1 Interrupt Flag

Value	Description
1	CLC1 interrupt has occurred (must be cleared in software)
0	CLC1 interrupt event has not occurred

Bit 4 – NCO1IF NCO1 Interrupt Flag

Value	Description
1	NCO1 interrupt has occurred (must be cleared in software)
0	NCO1 interrupt event has not occurred

Bit 3 – CCP2IF CCP2 Interrupt Flag


Value	CCP Mode
Value	Capture	Compare	PWM
`1`	Capture occurred (must be cleared in software)	Compare match occurred (must be cleared in software)	Output trailing edge occurred (must be cleared in software)
`0`	Capture did not occur	Compare match did not occur	Output trailing edge did not occur

Bit 2 – CCP1IF CCP1 Interrupt Flag


Value	CCP Mode
Value	Capture	Compare	PWM
`1`	Capture occurred (must be cleared in software)	Compare match occurred (must be cleared in software)	Output trailing edge occurred (must be cleared in software)
`0`	Capture did not occur	Compare match did not occur	Output trailing edge did not occur

Bit 1 – TMR6IF TMR6 Interrupt Flag

Value	Description
1	TMR6 interrupt has occurred (must be cleared in software)
0	TMR6 interrupt event has not occurred

Bit 0 – TMR4IF TMR4 Interrupt Flag

Value	Description
1	TMR4 interrupt has occurred (must be cleared in software)
0	TMR4 interrupt event has not occurred

Interrupt flag bits are set when an Interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable (GIE) bit. User software may ensure the appropriate interrupt flag bits are cleared before enabling an interrupt.