38.2 Standard Instruction Set

Table 38-3. Instruction Set
Mnemonic,

Operands

DescriptionCycles14-Bit OpcodeStatus

Affected

Notes
MSbLSb
BYTE-ORIENTED OPERATIONS
ADDWFf, dAdd WREG and f1
00
0111
dfff
ffff
C, DC, Z2
ADDWFCf, dAdd WREG and Carry bit to f1
11
1101
dfff
ffff
C, DC, Z2
ANDWFf, dAND WREG with f1
00
0101
dfff
ffff
Z2
ASRFf, dArithmetic Right Shift1
11
0111
dfff
ffff
C, Z2
LSLFf, dLogical Left Shift1
11
0101
dfff
ffff
C, Z2
LSRFf, dLogical Right Shift1
11
0110
dfff
ffff
C, Z2
CLRFfClear f1
00
0001
lfff
ffff
Z2
CLRWClear WREG1
00
0001
0000
00xx
Z
COMFf, dComplement f1
00
1001
dfff
ffff
Z2
DECFf, dDecrement f1
00
0011
dfff
ffff
Z2
INCFf, dIncrement f1
00
1010
dfff
ffff
Z2
IORWFf, dInclusive OR WREG with f1
00
0100
dfff
ffff
Z2
MOVFf, dMove f1
00
1000
dfff
ffff
Z2
MOVWFfMove WREG to f1
00
0000
1fff
ffff
None2
RLFf, dRotate Left f through Carry1
00
1101
dfff
ffff
C2
RRFf, dRotate Right f through Carry1
00
1100
dfff
ffff
C2
SUBWFf, dSubtract WREG from f1
00
0010
dfff
ffff
C, DC, Z2
SUBWFBf, dSubtract WREG from f with 
 Borrow1
11
1011
dfff
ffff
C, DC, Z2
SWAPFf, dSwap nibbles in f1
00
1110
dfff
ffff
None2
XORWFf, dExclusive OR WREG with f1
00
0110
dfff
ffff
Z2
BYTE-ORIENTED SKIP OPERATIONS
DECFSZf, dDecrement f, Skip if 01(2)
00
1011
dfff
ffff
None1, 2
INCFSZf, dIncrement f, Skip if 01(2)
00
1111
dfff
ffff
None1, 2
BIT-ORIENTED FILE REGISTER OPERATIONS
BCFf, bBit Clear f1
01
00bb
bfff
ffff
None2
BSFf, bBit Set f1
01
01bb
bfff
ffff
None2
BIT-ORIENTED SKIP OPERATIONS
BTFSCf, bBit Test f, Skip if Clear1(2)
01
10bb
bfff
ffff
None1, 2
BTFSSf, bBit Test f, Skip if Set1(2)
1010
11bb
bfff
ffff
None1, 2
LITERAL OPERATIONS
ADDLWkAdd literal and WREG1
11
1110
kkkk
kkkk
C, DC, Z
ANDLWkAND literal with WREG1
11
1001
kkkk
kkkk
Z
IORLWkInclusive OR literal with WREG1
11
1000
kkkk
kkkk
Z
MOVLBkMove literal to BSR1
00
000
0k
kkkk
None
MOVLPkMove literal to PCLATH1
11
0001
1kkk
kkkk
None
MOVLWkMove literal to W1
11
0000
kkkk
kkkk
None
SUBLWkSubtract W from literal1
11
1100
kkkk
kkkk
C, DC, Z
XORLWkExclusive OR literal with W1
11
1010
kkkk
kkkk
Z
CONTROL OPERATIONS
BRAkRelative Branch2
11
001k
kkkk
kkkk
None
BRWRelative Branch with WREG2
00
0000
0000
1011
None
CALLkCall Subroutine2
10
0kkk
kkkk
kkkk
None
CALLWCall Subroutine with WREG2
00
0000
0000
1010
None
GOTOkGo to address2
10
1kkk
kkkk
kkkk
None
RETFIEkReturn from interrupt2
00
0000
0000
1001
None
RETLWkReturn with literal in WREG2
11
0100
kkkk
kkkk
None
RETURNReturn from Subroutine2
00
0000
0000
1000
None
INHERENT OPERATIONS
CLRWDTClear Watchdog Timer1
00
0000
0110
0100
TO, PD
NOPNo Operation1
00
0000
0000
0000
None
RESETSoftware device Reset1
00
0000
0000
0001
None
SLEEPGo into Standby mode1
00
0000
0110
0011

TO, PD

TRISfLoad TRIS register with WREG1
00
0000
0110
0fff
None
C-COMPILER OPTIMIZED
ADDFSRn, kAdd Literal k to FSRn1
11
0001
0nkk
kkkk
None
MOVIWn, mmMove Indirect FSRn to WREG with pre/post inc/dec modifier, mm1
00
0000
0001
0nmm
Z2, 3
k[n]Move INDFn to WREG, Indexed Indirect.1
11
1111
0nkk
kkkk
Z2
MOVWIn, mmMove WREG to Indirect FSRn with pre/post inc/dec modifier, mm1
00
0000
0001
1nmm
None2, 3
k[n]Move WREG to INDFn, Indexed Indirect.1
11
1111
1nkk
kkkk
None2
Note:
  1. If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP.
  2. If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require one additional instruction cycle.
  3. Details on MOVIW and MOVWI instruction descriptions are available in the next section.