38.2.1 Standard Instruction Set 


ADDFSR	Add Literal to FSRn
Syntax:	[ label ] ADDFSR FSRn, k
Operands:	-32 ≤ k ≤ 31; n ∈ [ 0, 1]
Operation:	FSR(n) + k → FSR(n)
Status Affected:	None
Description:	The signed 6-bit literal ‘k’ is added to the contents of the FSRnH:FSRnL register pair. FSRn is limited to the range `0000h-FFFFh`. Moving beyond these bounds will cause the FSR to wrap-around.


ADDLW	Add Literal to W
Syntax:	[ label ] ADDLW k
Operands:	0 ≤ k ≤ 255
Operation:	(W) + k → (W)
Status Affected:	C, DC, Z
Description:	The contents of W are added to the 8-bit literal ‘k’ and the result is placed in W.


ADDWF	Add W to f
Syntax:	[ label ] ADDWF f, d
Operands:	0 ≤ f ≤ 127 d ∈ [0,1]
Operation:	(W) + (f) → dest
Status Affected:	C, DC, Z
Description:	Add the contents of the W register with register ‘f’. If ‘d’ is ‘`0`’, the result is stored in the W register. If ‘d’ is ‘`1`’, the result is stored back in register ‘f’.


ADDWFC	Add W and Carry Bit to f
Syntax:	[ label ] ADDWFC f {,d}
Operands:	0 ≤ f ≤ 127 d ∈ [0,1]
Operation:	(W) + (f) + (C) → dest
Status Affected:	C, DC, Z
Description:	Add W, the Carry flag and data memory location ‘f’. If ‘d’ is ‘`0`’, the result is placed in W. If ‘d’ is ‘`1`’, the result is placed in data memory location ‘f’.


ANDLW	AND Literal with W
Syntax:	[ label ] ANDLW k
Operands:	0 ≤ k ≤ 255
Operation:	(W) .AND. k → (W)
Status Affected:	Z
Description:	The contents of W are AND’ed with the 8-bit literal ‘k’. The result is placed in W.


ANDWF	AND W with f
Syntax:	[ label ] ANDWF f, d
Operands:	0 ≤ f ≤ 127 d ∈ [0,1]
Operation:	(W) .AND. (f) → dest
Status Affected:	Z
Description:	AND the W register with register ‘f’. If ‘d’ is ‘`0`’, the result is stored in the W register. If ‘d’ is ‘`1`’, the result is stored back in register ‘f’.


ASRF	Arithmetic Right Shift
Syntax:	[ label ] ASRF f, d
Operands:	0 ≤ f ≤ 127 d ∈ [0,1]
Operation:	(f[7]) → dest[7] (f[7:1]) → dest[6:0] (f[0]) → C
Status Affected:	C, Z
Description:	The contents of register ‘f’ are shifted one bit to the right through the Carry flag. The MSb remains unchanged. If ‘d’ is ‘`0`’, the result is placed in W. If ‘d’ is ‘`1`’, the result is stored back in register ‘f’. Register f → C


BCF	Bit Clear f
Syntax:	[ label ] BCF f, b
Operands:	0 ≤ f ≤ 127 0 ≤ b ≤ 7
Operation:	0 → f[b]
Status Affected:	None
Description:	Bit ‘b’ in register ‘f’ is cleared.


BRA	Relative Branch
Syntax:	[ label ] BRA label [ label ] BRA $+k
Operands:	-256 ≤ label - PC + ≤ 255 -256 ≤ k ≤ 255
Operation:	(PC) + 1 + k → PC
Status Affected:	None
Description:	Add the signed 9-bit literal ‘k’ to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 1 + k. This instruction is a two-cycle instruction. This branch has a limited range.


BRW	Relative Branch with W
Syntax:	[ label ] BRW
Operands:	None
Operation:	(PC) + (W) → PC
Status Affected:	None
Description:	Add the contents of W (unsigned) to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 1 + (W). This instruction is a two-cycle instruction.


BSF	Bit Set f
Syntax:	[ label ] BSF f, b
Operands:	0 ≤ f ≤ 127 0 ≤ b ≤ 7
Operation:	1 → (f[b])
Status Affected:	None
Description:	Bit ‘b’ in register ‘f’ is set.


BTFSC	Bit Test File, Skip If Clear
Syntax:	[ label ] BTFSC f, b
Operands:	0 ≤ f ≤ 127 0 ≤ b ≤ 7
Operation:	skip if (f[b]) = `0`
Status Affected:	None
Description:	If bit ‘b’ in register ‘f’ is ‘`1`’, the next instruction is executed. If bit ‘b’, in register ‘f’, is ‘`0`’, the next instruction is discarded, and a `NOP` is executed instead, making this a two-cycle instruction.


BTFSS	Bit Test File, Skip If Set
Syntax:	[ label ] BTFSS f, b
Operands:	0 ≤ f ≤ 127 0 ≤ b < 7
Operation:	skip if (f[b]) = `1`
Status Affected:	None
Description:	If bit ‘b’ in register ‘f’ is ‘`0`’, the next instruction is executed. If bit ‘b’ is ‘`1`’, then the next instruction is discarded, and a `NOP` is executed instead, making this a two-cycle instruction.


CALL	Subroutine Call
Syntax:	[ label ] CALL k
Operands:	0 ≤ k ≤ 2047
Operation:	(PC) + 1 → TOS, k → PC[10:0], (PCLATH[6:3]) → PC[14:11]
Status Affected:	None
Description:	Call Subroutine. First, return address (PC + 1) is pushed onto the stack. The 11-bit immediate address is loaded into PC bits [10:0]. The upper bits of the PC are loaded from PCLATH. `CALL` is a two-cycle instruction.


CALLW	Subroutine Call with W
Syntax:	[ label ] CALLW
Operands:	None
Operation:	(PC) + 1 → TOS, (W) → PC[7:0], (PCLATH[6:0]) → PC[14:8]
Status Affected:	None
Description:	Subroutine call with W. First, the return address (PC + 1) is pushed onto the return stack. Then, the contents of W is loaded into PC[7:0], and the contents of PCLATH into PC[14:8]. `CALLW` is a two-cycle instruction.


CLRF	Clear f
Syntax:	[ label ] CLRF f
Operands:	0 ≤ f ≤ 127
Operation:	000h → f 1 → Z
Status Affected:	Z
Description:	The contents of register ‘f’ are cleared and the Z bit is set.


CLRW	Clear W
Syntax:	[ label ] CLRW
Operands:	None
Operation:	00h → (W) 1 → Z
Status Affected:	Z
Description:	W register is cleared. Zero (Z) bit is set.


CLRWDT	Clear Watchdog Timer
Syntax:	[ label ] CLRWDT
Operands:	None
Operation:	00h → WDT, 00h → WDT prescaler, 1 → TO, 1 → PD
Status Affected:	TO, PD
Description:	`CLRWDT` instruction resets the  Watchdog Timer. It also resets the prescaler of the WDT. Status bits, TO and PD, are set.


COMF	Complement f
Syntax:	[ label ] COMF f, d
Operands:	0 ≤ f ≤ 127 d ∈ [0,1]
Operation:	(f) → dest
Status Affected:	Z
Description:	The contents of register ‘f’ are complemented. If ‘d’ is ‘`0`’, the result is stored in W. If ‘d’ is ‘`1`’, the result is stored back in register ‘f’.


DECF	Decrement f
Syntax:	[ label ] DECF f, d
Operands:	0 ≤ f ≤ 127 d ∈ [0,1]
Operation:	(f) – 1 → dest
Status Affected:	Z
Description:	Decrement register ‘f’. If ‘d’ is ‘`0`’, the result is stored in the W register. If ‘d’ is ‘`1`’, the result is stored back in register ‘f’.


DECFSZ	Decrement f, Skip If 0
Syntax:	[ label ] DECFSZ f, d
Operands:	0 ≤ f ≤ 127 d ∈ [0,1]
Operation:	(f) – 1 → dest,  skip if result = `0`
Description:	The contents of register ‘f’ are decremented. If ‘d’ is ‘`0`’, the result is placed in the W register. If ‘d’ is ‘`1`’, the result is placed back in register ‘f’. If the result is ‘`1`’, the next instruction is executed. If the result is ‘`0`’, then a `NOP` is executed instead, making it a two-cycle instruction.


GOTO	Unconditional Branch
Syntax:	[ label ] GOTO k
Operands:	0 ≤ k ≤ 2047
Operation:	k → PC[10:0] PCLATH[6:3] → PC[14:11]
Status Affected:	None
Description:	`GOTO` is an unconditional branch. The 11-bit immediate value is loaded into PC bits [10:0]. The upper bits of PC are loaded from PCLATH[4:3]. `GOTO` is a two-cycle instruction.


INCF	Increment f
Syntax:	[ label ] INCF f, d
Operands:	0 ≤ f ≤ 127 d ∈ [0,1]
Operation:	(f) + 1 → dest
Status Affected:	Z
Description:	The contents of register ‘f’ are incremented. If ‘d’ is ‘`0`’, the result is placed in the W register. If ‘d’ is ‘`1`’, the result is placed back in register ‘f’.


INCFSZ	Increment f, Skip If 0
Syntax:	[ label ] INCFSZ f, d
Operands:	0 ≤ f ≤ 127 d ∈ [0,1]
Operation:	(f) + 1 → dest, skip if result = `0`
Status Affected:	None
Description:	The contents of register ‘f’ are incremented. If ‘d’ is ‘`0`’, the result is placed in the W register. If ‘d’ is ‘`1`’, the result is placed back in register ‘f’. If the result is ‘`1`’, the next instruction is executed. If the result is ‘`0`’, a `NOP` is executed instead, making it a two-cycle instruction.


IORLW	Inclusive OR Literal with W
Syntax:	[ label ] IORLW k
Operands:	0 ≤ k ≤ 255
Operation:	(W) .OR. k → (W)
Status Affected:	Z
Description:	The contents of W are ORed with the 8-bit literal ‘k’. The result is placed in W.


IORWF	Inclusive OR W with f
Syntax:	IORWF f, d
Operands:	0 ≤ f ≤ 127 d ∈ [0,1]
Operation:	(W) .OR. (f) → dest
Status Affected:	Z
Description:	Inclusive OR the W register with register ‘f’. If ‘d’ is ‘`0`’, the result is placed in the W register. If ‘d’ is ‘`1`’, the result is placed back in register ‘f’.


LSLF	Logical Left Shift
Syntax:	[ label ] LSLF f {,d}
Operands:	0 ≤ f ≤ 127 d ∈ [0,1]
Operation:	(f[7]) → C (f[6:0]) → dest[7:1] 0 → dest[0]
Status Affected:	C, Z
Description:	The contents of register ‘f’ are shifted one bit to the left through the Carry flag. A ‘`0`’ is shifted into the LSb. If ‘d’ is ‘`0`’, the result is placed in W. If ‘d’ is ‘`1`’, the result is stored back in register ‘f’. C ← Register f ← 0


LSRF	Logical Right Shift
Syntax:	[ label ] LSRF f {,d}
Operands:	0 ≤ f ≤ 127 d ∈ [0,1]
Operation:	0 → dest[7] (f[7:1]) → dest[6:0], (f[0]) → C
Status Affected:	C, Z
Description:	The contents of register ‘f’ are shifted one bit to the right through the Carry flag. A ‘`0`’ is shifted into the MSb. If ‘d’ is ‘`0`’, the result is placed in W. If ‘d’ is ‘`1`’, the result is stored back in register ‘f’. 0 → Register f → C


MOVF	Move f
Syntax:	[ label ] MOVF f, d
Operands:	0 ≤ f ≤ 127 d ∈ [0,1]
Operation:	f → dest
Status Affected:	Z
Description:	The contents of register f is moved to a destination dependent upon the status of d. If d = `0`, destination is W register. If d = `1`, the destination is file register f itself. d = `1` is useful to test a file register since status flag Z is affected.
Words:	1
Cycles:	1


Example:	`MOVF FSR, 0`
After Instruction W = value in FSR register Z = `1`


MOVIW	Move INDFn to W
Syntax:	[ label ] MOVIW ++FSRn [ label ] MOVIW --FSRn [ label ] MOVIW FSRn++ [ label ] MOVIW FSRn-- [ label ] MOVIW k[FSRn]
Operands:	n ∈ [0,1] mm ∈ [00,01,10,11] -32 ≤ k ≤ 31
Operation:	INDFn → (W) Effective address is determined by FSR + 1 (preincrement) FSR - 1 (predecrement) FSR + k (relative offset) After the Move, the FSR value will be either: FSR + 1 (all increments) FSR - 1 (all decrements) Unchanged
Status Affected:	Z
	MODE		SYNTAX	mm
	Preincrement		++FSRn	`00`
	Predecrement		--FSRn	`01`
	Postincrement		FSRn++	`10`
	Postdecrement		FSRn--	`11`
Description:	This instruction is used to move data between W and one of the indirect registers (INDFn). Before/after this move, the pointer (FSRn) is updated by pre/post incrementing/decrementing it. The INDFn registers are not physical registers. Any instruction that accesses an INDFn register actually accesses the register at the address specified by the FSRn. FSRn is limited to the range `0000h - FFFFh`. Incrementing/decrementing it beyond these bounds will cause it to wrap-around.


MOVLB	Move Literal to BSR
Syntax:	[ label ] MOVLB k
Operands:	0 ≤ k ≤ 127
Operation:	k → BSR
Status Affected:	None
Description:	The 6-bit literal ‘k’ is loaded into the Bank Select Register (BSR).


MOVLP	Move Literal to PCLATH
Syntax:	[ label ] MOVLP k
Operands:	0 ≤ k ≤ 127
Operation:	k → PCLATH
Status Affected:	None
Description:	The 7-bit literal ‘k’ is loaded into the PCLATH register.


MOVLW	Move Literal to W
Syntax:	[ label ] MOVLW k
Operands:	0 ≤ k ≤ 255
Operation:	k → (W)
Status Affected:	None
Description:	The 8-bit literal ‘k’ is loaded into W register. The “don’t cares” will assemble as ‘`0`’s.
Words:	1
Cycles:	1


Example:	`MOVLW`	`5Ah`
After Instruction W = 5Ah


MOVWF	Move W to f
Syntax:	[ label ] MOVWF f
Operands:	0 ≤ f ≤ 127
Operation:	(W) → f
Status Affected:	None
Description:	Move data from W to register ‘f’.
Words:	1
Cycles:	1


Example:	`MOVWF`	`LATA`
Before Instruction LATA = `FFh` W = `4Fh` After Instruction LATA = `4Fh` W = `4Fh`


MOVWI	Move W to INDFn
Syntax:	[ label ] MOVWI ++FSRn [ label ] MOVWI --FSRn [ label ] MOVWI FSRn++ [ label ] MOVWI FSRn-- [ label ] MOVWI k[FSRn]
Operands:	n ∈ [0,1] mm ∈ [00,01,10,11] -32 ≤ k ≤ 31
Operation:	(W) → INDFn Effective address is determined by FSR + 1 (preincrement) FSR - 1 (predecrement) FSR + k (relative offset) After the Move, the FSR value will be either: FSR + 1 (all increments) FSR - 1 (all decrements) Unchanged
Status Affected:	None
	MODE		SYNTAX	mm
	Preincrement		++FSRn	`00`
	Predecrement		--FSRn	`01`
	Postincrement		FSRn++	`10`
	Postdecrement		FSRn--	`11`
Description:	This instruction is used to move data between W and one of the indirect registers (INDFn). Before/after this move, the pointer (FSRn) is updated by pre/post incrementing/decrementing it. The INDFn registers are not physical registers. Any instruction that accesses an INDFn register actually accesses the register at the address specified by the FSRn. FSRn is limited to the range `0000h-FFFFh`. Incrementing/decrementing it beyond these bounds will cause it to wrap-around. The increment/decrement operation on FSRn WILL NOT affect any Status bits.


NOP	No Operation
Syntax:	[ label ] NOP
Operands:	None
Operation:	No operation
Status Affected:	None
Description:	No operation.
Words:	1
Cycles:	1


Example:	`NOP`
None.


RESET	Software Reset
Syntax:	[ label ] RESET
Operands:	None
Operation:	Execute a device Reset. Resets the RI flag of the PCON register.
Status Affected:	None
Description:	This instruction provides a way to execute a hardware Reset by software.


RETFIE	Return from Interrupt
Syntax:	[ label ] RETFIE k
Operands:	None
Operation:	(TOS) → PC, 1 → GIE
Status Affected:	None
Description:	Return from Interrupt. Stack is POPed and Top-of-Stack (TOS) is loaded in the PC. Interrupts are enabled by setting the Global Interrupt Enable bit, GIE (INTCON[7]). This is a two-cycle instruction.
Words:	1
Cycles:	2


Example:	`RETFIE`
After Interrupt PC = TOS GIE = `1`


RETLW	Return Literal to W
Syntax:	[ label ] RETLW k
Operands:	0 ≤ k ≤ 255
Operation:	k → (W), (TOS) → PC,
Status Affected:	None
Description:	The W register is loaded with the 8-bit literal ‘k’. The program counter is loaded from the top of the stack (the return address). This is a two-cycle instruction.
Words:	1
Cycles:	2


Example: CALL TABLE ; W contains table ; offset value ; W now has ; table value  : TABLE ADDWF PC ; W = offset RETLW k1 ; Begin table RETLW k2 ; : : RETLW kn ; End of table
Before Instruction W = 07h After Instruction W = value of k8


RETURN	Return from Subroutine
Syntax:	[ label ] RETURN
Operands:	None
Operation:	(TOS) → PC,
Status Affected:	None
Encoding:	0000	0000	0001	001s
Description:	Return from subroutine. The stack is POPped and the top of the stack (TOS) is loaded into the Program Counter. This is a two-cycle instruction.


RLF	Rotate Left f through Carry
Syntax:	[ label ] RLF f, d
Operands:	0 ≤ f ≤ 127 d ∈ [0,1]
Operation:	(f[n]) → dest[n + 1], (f[7]) → C, (C) → dest[0]
Status Affected:	C
Encoding:	0011	01da	ffff	ffff
Description:	The contents of register ‘f’ are rotated one bit to the left through the Carry flag. If ‘d’ is ‘`0`’, the result is placed in W. If ‘d’ is ‘`1`’, the result is stored back in register ‘f’ (default).
Words:	1
Cycles:	1


Example:	`RLF`	`REG1, 0`
Before Instruction REG1 = `1110 0110` C = `0` After Instruction REG = `1110 0110` W = `1100 1100` C = `1`


RRF	Rotate Right f through Carry
Syntax:	[ label ] RRF f, d
Operands:	0 ≤ f ≤ 127 d ∈ [0,1]
Operation:	(f[n]) → dest[n – 1], (f[0]) → C, (C) → dest[7]
Status Affected:	C
Description:	The contents of register ‘f’ are rotated one bit to the right through the Carry flag. If ‘d’ is ‘`0`’, the result is placed in W. If ‘d’ is ‘`1`’, the result is placed back in register ‘f’ (default).


SLEEP	Enter Sleep Mode
Syntax:	[ label ] SLEEP
Operands:	None
Operation:	00h → WDT, 0 → WDT prescaler, 1 → TO, 0 → PD
Status Affected:	TO, PD
Description:	The Power-Down (PD) Status bit is cleared. The Time-Out (TO) Status bit is set. Watchdog Timer and its prescaler are cleared.


SUBLW	Subtract W from Literal
Syntax:	[ label ] SUBLW k
Operands:	0 ≤ k ≤ 255
Operation:	k – (W) → (W)
Status Affected:	C, DC, Z
Description	The W register is subtracted (two’s complement method) from the 8-bit literal ‘k’. The result is placed in the W register. C = `0`, W > k C = `1`, W ≤ k DC = `0`, W[3:0] > k[3:0] DC = `1`, W[3:0] ≤ k[3:0]


SUBWF	Subtract W from f
Syntax:	[ label ] SUBWF f, d
Operands:	0 ≤ f ≤ 127 d ∈ [0,1]
Operation:	(f) - (W) → (dest)
Status Affected:	C, DC, Z
Description	Subtract (two’s complement method) W register from register ‘f’. If ‘d’ is ‘`0`’, the result is stored in the W register. If ‘d’ is ‘`1`’, the result is stored back in register ‘f. C = `0`, W > f C = `1`, W ≤ f DC = `0`, W[3:0] > f[3:0] DC = `1`, W[3:0] ≤ f[3:0]


SUBWFB	Subtract W from f with Borrow
Syntax:	[ label ] SUBFWB f {,d}
Operands:	0 ≤ f ≤ 127 d ∈ [0,1]
Operation:	(W) – (f) – (B) → dest
Status Affected:	C, DC, Z
Description:	Subtract W and the Borrow flag (Carry) from register ‘f’ (two’s complement method). If ‘d’ is ‘`0`’, the result is stored in W. If ‘d’ is ‘`1`’, the result is stored back in register ‘f’.


SWAPF	Swap Nibbles in f
Syntax:	[ label ] SWAPF f, d
Operands:	0 ≤ f ≤ 127 d ∈ [0,1]
Operation:	(f[3:0]) → dest[7:4], (f[7:4]) → dest[3:0]
Status Affected:	None
Description:	The upper and lower nibbles of register ‘f’ are exchanged. If ‘d’ is ‘`0`’, the result is placed in W. If ‘d’ is ‘`1`’, the result is placed in register ‘f’ (default).


TRIS	Load TRIS Register with W
Syntax:	[ label ] TRIS f
Operands:	5 ≤ f ≤ 7
Operation:	(W) → TRIS register ‘f’
Status Affected:	None
Description:	Move data from W register to TRIS register. When ‘f’ = 5, TRISA is loaded. When ‘f’ = 6, TRISB is loaded. When ‘f’ = 7, TRISC is loaded.


XORLW	Exclusive OR Literal with W
Syntax:	[ label ] XORLW k
Operands:	0 ≤ k ≤ 255
Operation:	(W) .XOR. k → (W)
Status Affected:	Z
Description:	The contents of W are XORed with the 8-bit literal ‘k’. The result is placed in W.


XORWF	Exclusive OR W with f
Syntax:	[ label ] XORWF f, d
Operands:	0 ≤ f ≤ 127 d ∈ [0,1]
Operation:	(W) .XOR. (f) → dest
Status Affected:	Z
Description:	Exclusive OR the contents of the W register with register ‘f’. If ‘d’ is ‘`0`’, the result is stored in the W register. If ‘d’ is ‘`1`’, the result is stored back in register ‘f’.

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