28.8.8 CLCnGLS0

CLCn Gate1 Logic Select Register
Name: CLCnGLS0
Offset: 0x0592

Bit 76543210 
 G1D4TG1D4NG1D3TG1D3NG1D2TG1D2NG1D1TG1D1N 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset xxxxxxxx 

Bits 1, 3, 5, 7 – G1DyT dyT: Gate1 Data ‘y’ True (noninverted)

Reset States: 
POR/BOR = xxxx
All Other Resets = uuuu
ValueDescription
1 dyT is gated into g1
0 dyT is not gated into g1

Bits 0, 2, 4, 6 – G1DyN dyN: Gate1 Data ‘y’ Negated (inverted)

Reset States: 
POR/BOR = xxxx
All Other Resets = uuuu
ValueDescription
1 dyN is gated into g1
0 dyN is not gated into g1