19.2 PPS Inputs

Each digital peripheral has a dedicated PPS Peripheral Input Selection (xxxPPS) register with which the input pin to the peripheral is selected. Devices that have 20 leads or less (8/14/16/20) allow PPS routing to any I/O pin, while devices with 28 leads or more allow PPS routing to I/Os contained within two ports (see the table below). The outputs of the Signal Routing Port (SRPORT) can also be used as inputs to other peripherals using PPS.

Important: The notation “xxx” in the generic register name is a placeholder for the peripheral identifier. For example, xxx = T0CKI for the T0CKIPPS register.

Multiple peripherals can operate from the same source simultaneously. Port reads always return the pin level regardless of peripheral PPS selection. If a pin also has analog functions associated, the ANSEL bit for that pin must be cleared to enable the digital input buffer.

Table 19-1. PPS Input Selection Table
Peripheral	PPS Input Register	Default Pin Selection at POR		Register Reset Value at POR
Peripheral	PPS Input Register	14/16-Pin Devices	20-Pin Devices	14/16-Pin Devices	20-Pin Devices
External Interrupt	INTPPS	RA2		`‘b00 010`
Timer0 Clock	T0CKIPPS	RA2		`‘b00 010`
Timer1 Clock	T1CKIPPS	RA5		`‘b00 101`
Timer1 Gate	T1GPPS	RA4		`‘b00 100`
Timer3 Clock	T3CKIPPS	RC5		`‘b10 101`
Timer3 Gate	T3GPPS	RC4		`‘b10 100`
Timer2 Input	T2INPPS	RA5		`‘b00 101`
Timer4 Input	T4INPPS	RC1		`‘b10 001`
CCP1	CCP1PPS	RC5		`‘b10 101`
CCP2	CCP2PPS	RC3		`‘b10 011`
PWM Input 0	PWMIN0PPS	RC5		`‘b10 101`
PWM Input 1	PWMIN1PPS	RC3		`‘b10 011`
PWM1 External Reset	PWMIN1ERSPPS	RA5		`‘b00 101`
PWM2 External Reset	PWMIN2ERSPPS	RC1		`‘b10 001`
CWG1	CWG1PPS	RA2		`‘b00 010`
CLCIN0	CLCIN0PPS	RC3	RA2	`‘b10 011`	`‘b00 010`
CLCIN1	CLCIN1PPS	RC4	RC3	`‘b10 100`	`‘b10 011`
CLCIN2	CLCIN2PPS	RC1	RB4	`‘b10 001`	`‘b01 100`
CLCIN3	CLCIN3PPS	RA5	RB5	`‘b00 101`	`‘b01 101`
SCL1/SCK1	SSP1CLKPPS⁽¹⁾	RC0	RB6	`‘b10 000`	`‘b01 110`
SDA1/SDI1	SSP1DATPPS⁽¹⁾	RC1	RB4	`‘b10 001`	`‘b01 100`
SS1	SSP1SSPPS	RC3	RC6	`‘b10 011`	`‘b10 110`
SCL2/SCK2	SSP2CLKPPS⁽¹⁾	RC4	RB7	`‘b10 100`	`‘b01 111`
SDA2/SDI2	SSP2DATPPS⁽¹⁾	RC5	RB5	`‘b10 101`	`‘b01 101`
SS2	SSP2SSPPS	RA0	RA1	`‘b00 000`	`‘b00 001`
RX1/DT1	RX1PPS	RC5	RB5	`‘b10 101`	`‘b01 101`
CK1	CK1PPS	RC4	RB7	`‘b10 100`	`‘b01 111`
RX2/DT2	RX2PPS	RC1		`‘b010 001`
CK2	CK2PPS	RC0		`‘b010 000`
ADC Conversion Trigger	ADACTPPS	RC2		`‘b010 010`
Signal Routing Port Input 0	PORTWIN0PPS	RA0		`‘b000 000`
Signal Routing Port Input 1	PORTWIN1PPS	RA1		`‘b000 001`
Signal Routing Port Clock Input	PORTWCLKPPS	RA2		`‘b000 010`
Analog Peripheral Manager	APMCLKPPS	RC4		`‘b010 100`

Note:

Bidirectional pin. The corresponding output must select the same pin.