Figure 38-135. Falling Edge
Response Time vs. VDD (VCM =
VDD/2, CTRLA.POWER =
0x00)
Figure 38-136. Rising Edge
Response Time vs. VDD (VCM =
VDD/2, CTRLA.POWER =
0x00)
Figure 38-137. Falling Edge
Response Time vs. VDD (VCM =
VDD/2, CTRLA.POWER =
0x01)
Figure 38-138. Rising Edge
Response Time vs. VDD (VCM =
VDD/2, CTRLA.POWER =
0x01)
Figure 38-139. Falling Edge
Response Time vs. VDD (VCM =
VDD/2, CTRLA.POWER =
0x02)
Figure 38-140. Rising Edge
Response Time vs. VDD (VCM =
VDD/2, CTRLA.POWER =
0x02)
Figure 38-141. Input Offset
vs. Common Mode Voltage (VDD = 2.0V)
Figure 38-142. Input
Hysteresis vs. Common Mode Voltage (VDD =
2.0V)
Figure 38-143. Input Offset
vs. Common Mode Voltage (VDD = 3.0V)
Figure 38-144. Input
Hysteresis vs. Common Mode Voltage (VDD =
3.0V)
Figure 38-145. Input Offset
vs. Common Mode Voltage (VDD = 5.5V)
Figure 38-146. Input
Hysteresis vs. Common Mode Voltage (VDD =
5.5V)
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