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AVR® DA Family
Introduction
AVR® DA(S) Family Overview
1 Memory Overview
2 Peripheral Overview
Security Concept
Features
1 Block Diagram
2 Pinout
2.1 28-Pin SPDIP, SSOP and SOIC
2.2 32-Pin VQFN and TQFP
2.3 48-Pin VQFN and TQFP
2.4 64-Pin VQFN and TQFP
3 I/O Multiplexing and Considerations
3.1 I/O Multiplexing
4 Hardware Guidelines
4.1 General Guidelines
4.2 Connection for Power Supply
4.3 Connection for RESET
4.4 Connection for UPDI Programming
4.5 Connecting External Crystal Oscillators
4.6 Connection for External Voltage Reference
5 Conventions
5.1 Numerical Notation
5.2 Memory Size and Type
5.3 Frequency and Time
5.4 Registers and Bits
5.5 ADC Parameter Definitions
6 AVR® CPU
6.1 Features
6.2 Overview
6.3 Architecture
6.4 Functional Description
6.5 Register Summary
6.6 Register Description
7 Memories
7.1 Overview
7.2 Memory Map
7.3 In-System Reprogrammable Flash Program Memory
7.4 Program and Debug Interface Disable (PDID)
7.5 SRAM Data Memory
7.6 EEPROM Data Memory
7.7 SIGROW - Signature Row
7.8 USERROW - User Row
7.9 FUSE - Configuration and User Fuses
7.10 LOCK - Memory Sections Access Protection
7.11 I/O Memory
8 Peripherals and Architecture
8.1 Peripheral Address Map
8.2 Interrupt Vector Mapping
8.3 SYSCFG - System Configuration
9 GPR - General Purpose Registers
9.1 Register Summary
9.2 Register Description
10 NVMCTRL - Nonvolatile Memory Controller
10.1 Features
10.2 Overview
10.3 Functional Description
10.4 Register Summary
10.5 Register Description
11 CLKCTRL - Clock Controller
11.1 Features
11.2 Overview
11.3 Functional Description
11.4 Register Summary
11.5 Register Description
12 SLPCTRL - Sleep Controller
12.1 Features
12.2 Overview
12.3 Functional Description
12.4 Register Summary
12.5 Register Description
13 RSTCTRL - Reset Controller
13.1 Features
13.2 Overview
13.3 Functional Description
13.4 Register Summary
13.5 Register Description
14 CPUINT - CPU Interrupt Controller
14.1 Features
14.2 Overview
14.3 Functional Description
14.4 Register Summary
14.5 Register Description
15 EVSYS - Event System
15.1 Features
15.2 Overview
15.3 Functional Description
15.4 Register Summary
15.5 Register Description
16 PORTMUX - Port Multiplexer
16.1 Overview
16.2 Register Summary
16.3 Register Description
17 PORT - I/O Pin Configuration
17.1 Features
17.2 Overview
17.3 Functional Description
17.4 Register Summary - PORTx
17.5 Register Description - PORTx
17.6 Register Summary - VPORTx
17.7 Register Description - VPORTx
18 BOD - Brown-out Detector
18.1 Features
18.2 Overview
18.3 Functional Description
18.4 Register Summary
18.5 Register Description
19 VREF - Voltage Reference
19.1 Features
19.2 Overview
19.3 Functional Description
19.4 Register Summary
19.5 Register Description
20 WDT - Watchdog Timer
20.1 Features
20.2 Overview
20.3 Functional Description
20.4 Register Summary
20.5 Register Description
21 TCA - 16-bit Timer/Counter Type A
21.1 Features
21.2 Overview
21.3 Functional Description
21.4 Register Summary - Single Mode
21.5 Register Description - Single Mode
21.6 Register Summary - Split Mode
21.7 Register Description - Split Mode
22 TCB - 16-Bit Timer/Counter Type B
22.1 Features
22.2 Overview
22.3 Functional Description
22.4 Register Summary
22.5 Register Description
23 TCD - 12-Bit Timer/Counter Type D
23.1 Features
23.2 Overview
23.3 Functional Description
23.4 Register Summary
23.5 Register Description
24 RTC - Real-Time Counter
24.1 Features
24.2 Overview
24.3 Clocks
24.4 RTC Functional Description
24.5 PIT Functional Description
24.6 Crystal Error Correction
24.7 Events
24.8 Interrupts
24.9 Sleep Mode Operation
24.10 Synchronization
24.11 Debug Operation
24.12 Register Summary
24.13 Register Description
25 USART - Universal Synchronous and Asynchronous Receiver and Transmitter
25.1 Features
25.2 Overview
25.3 Functional Description
25.4 Register Summary
25.5 Register Description
26 SPI - Serial Peripheral Interface
26.1 Features
26.2 Overview
26.3 Functional Description
26.4 Register Summary
26.5 Register Description
27 TWI - Two-Wire Interface
27.1 Features
27.2 Overview
27.3 Functional Description
27.4 Register Summary
27.5 Register Description
28 CRCSCAN - Cyclic Redundancy Check Memory Scan
28.1 Features
28.2 Overview
28.3 Functional Description
28.4 Register Summary
28.5 Register Description
29 CCL - Configurable Custom Logic
29.1 Features
29.2 Overview
29.3 Functional Description
29.4 Register Summary
29.5 Register Description
30 AC - Analog Comparator
30.1 Features
30.2 Overview
30.3 Functional Description
30.4 Register Summary
30.5 Register Description
31 ADC - Analog-to-Digital Converter
31.1 Features
31.2 Overview
31.3 Functional Description
31.4 Register Summary
31.5 Register Description
32 DAC - Digital-to-Analog Converter
32.1 Features
32.2 Overview
32.3 Functional Description
32.4 Register Summary
32.5 Register Description
33 PTC - Peripheral Touch Controller
33.1 Features
33.2 Overview
33.3 Block Diagram
33.4 Signal Description
33.5 System Dependencies
33.6 Functional Description
34 ZCD - Zero-Cross Detector
34.1 Features
34.2 Overview
34.3 Functional Description
34.4 Register Summary
34.5 Register Description
35 UPDI - Unified Program and Debug Interface
35.1 Features
35.2 Overview
35.3 Functional Description
35.4 Register Summary
35.5 Register Description
36 Instruction Set Summary
37 Electrical Characteristics
37.1 Disclaimer
37.2 Absolute Maximum Ratings
37.3 Standard Operating Conditions
37.4 Supply Voltage
37.5 Power Consumption
37.6 Peripherals Power Consumption
37.7 I/O Pins
37.8 Memory Programming Specifications
37.9 Thermal Specifications
37.10 CLKCTRL
37.11 RST and BOD
37.12 VREF
37.13 USART
37.14 SPI
37.15 TWI
37.16 DAC
37.17 ADC
37.18 AC
37.19 PTC
37.20 ZCD
37.21 UPDI
38 Characteristics Graphs
38.1 Power Consumption
38.2 Peripheral Power Consumption
38.3 CLKCTRL
38.4 Reset Controller
38.5 I/O Pins
38.6 VREF
38.7 ADC
38.8 Temperature Sensor
38.9 AC
38.10 DAC
38.11 ZCD
39 Ordering Information
40 Package Drawings
40.1 Online Package Drawings
40.2 Package Marking Information
40.3 28-Pin SPDIP
40.4 28-Pin SOIC
40.5 28-Pin SSOP
40.6 32-Pin VQFN
40.7 32-Pin VQFN Wettable Flanks
40.8 32-Pin TQFP
40.9 48-Pin VQFN
40.10 48-Pin VQFN Wettable Flanks
40.11 48-Pin TQFP
40.12 64-Pin VQFN
40.13 64-Pin VQFN Wettable Flanks
40.14 64-Pin TQFP
41 Data Sheet Revision History
41.1 Rev. E - 09/2024
41.2 Rev. D - 12/2023
41.3 Rev. C - 06/2021
41.4 Rev. B - 07/2020
41.5 Rev. A - 03/2020
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