32.3.3 Sleep Mode Operation

If the Run in Standby Mode (RUNSTDBY) bit in the Control A (CTRLA) register is written to ‘1’, the DAC will continue to operate in Standby sleep mode. If the RUNSTDBY bit is written to ‘0’, the DAC will automatically be disabled in Standby sleep mode.

If the conversion is stopped in Standby sleep mode, the DAC and the output buffer are disabled to reduce power consumption. When the device exits Standby sleep mode, the DAC and the output buffer (if the OUTEN bit in CTRLA register is written to ‘1’) are enabled again. For this reason, a certain start-up time is required before a new conversion is initiated. Refer to the Electrical Characteristics section for details on start-up time.

In Power-Down sleep mode, the DAC and the output buffer are disabled to reduce power consumption.