6.2 Reset

The Reset logic generates proper sequence to the device during Reset events. The Reset sources include external Reset, power-up Reset, and Watchdog Timer (WDT). The IS2083 SoC provides a WDT to Reset the chip. In addition, it has an integrated Power-on Reset (POR) circuit that resets all circuits to a known Power On state. This action can also be driven by an external Reset signal, which is used to control the device externally by forcing it into a POR state. The following figure illustrates the system behavior upon a RST_N event.

Note: The Reset (RST_N) is an active-low signal and can be utilized based on the application needs, otherwise, it can be left floating.
Figure 6-3. Timing Sequence of Reset Trigger
Note: RST_N pin has an internal pull-up, thus, RST_N signal will transition to high again upon releasing the RST_N button. This is an expected behavior of RST_N signal.
Figure 6-4. Timing Sequence of Power Drop Protection
Timing sequence of power drop protection:
  • It is recommended to use the battery to provide the power supply at BAT_IN.
  • If an external power source or a power adapter is utilized to provide power to BAT_IN, it is recommended to use a voltage supervisor Integrated Circuit (IC).
  • The Reset IC output pin, RST_N, must be open drain type and threshold voltage as 2.93V.
  • The RST_N signal must be fully pulled low before SYS_PWR power drop to 2.7V.