38.5.1.6 System Clock

Table 38-15. System Clock Timing Characteristics
Symbol	Description	Min.	Typ. ✝	Max.	Unit
f_{CLK_MAIN}	Main clock frequency^(1,2)	—	—	24	MHz
f_CY	Instruction clock frequency	—	f_{CLK_MAIN}	—	MHz
T_CY	Instruction period⁽³⁾	41.6	1/f_CY	—	ns
✝ Data in the “Typ.” column is at T_A = 25°C and V_DD = 3.0V unless otherwise specified. These parameters are not tested and are for design guidance only. Note: The main clock frequency (CLK_MAIN) is configured by the Clock Select (CLKSEL) bit field, as described in the CLKCTRL - Clock Controller section. The main clock frequency (CLK_MAIN) must meet the voltage requirements defined in 38.3 Standard Operating Conditions . The Instruction Cycle Period (T_CY) is identical to the input oscillator time-base period. All specified values are based on characterization data for that particular oscillator type, under standard operating conditions with the device executing code. Exceeding these specified limits may result in incorrect code execution and/or higher than expected current consumption. All devices are tested to operate at ‘min’ values with an external clock applied to the EXTCLK pin. The ‘max’ cycle time limit is ‘DC’ (no clock) for all devices when using an external clock input.

f_{CLK_MAIN}

Main clock frequency^(1,2)

—

24

MHz

f_CY

Instruction clock frequency

—

f_{CLK_MAIN}

—

MHz

T_CY

Instruction period⁽³⁾

41.6

1/f_CY

—

ns

✝ Data in the “Typ.” column is at T_A = 25°C and V_DD = 3.0V unless otherwise specified. These parameters are not tested and are for design guidance only.

Note:

The main clock frequency (CLK_MAIN) is configured by the Clock Select (CLKSEL) bit field, as described in the CLKCTRL - Clock Controller section.
The main clock frequency (CLK_MAIN) must meet the voltage requirements defined in 38.3 Standard Operating Conditions .
The Instruction Cycle Period (T_CY) is identical to the input oscillator time-base period. All specified values are based on characterization data for that particular oscillator type, under standard operating conditions with the device executing code. Exceeding these specified limits may result in incorrect code execution and/or higher than expected current consumption. All devices are tested to operate at ‘min’ values with an external clock applied to the EXTCLK pin. The ‘max’ cycle time limit is ‘DC’ (no clock) for all devices when using an external clock input.