2.4 Ethernet Driver Library

• union eir_t

  ENC28J60 EIR register.

• union phstat2_t

  ENC28J60 PHSTAT2 register.

• union receiveStatusVector_t

  ENC28J60 receive status vector.

• #define ETH_NCS_HIGH() do{ETH_CS_SetHigh();} while(0)

  Sets Ethernet Chip Select to high.

• #define ETH_NCS_LOW() do{ETH_CS_SetLow();} while(0)

  Sets Ethernet Chip Select to low.

• #define ETH_SPI_READ8() SPI1_Host.ByteExchange(0)

  Reads the SPI byte.

• #define ETH_SPI_WRITE8(a) SPI1_Host.ByteExchange(a)

  Writes the SPI byte.

• #define ETH_WRITE_IN_PROGRESS (0x0001 << 0)

  Packet write in progress, not ready for transmit.

• #define ETH_TX_QUEUED (0x0001 << 1)

  Packet complete, in queue for transmit.

• #define ETH_ALLOCATED (0x0001 << 2)

  Flag for pool management. Set to either free or allocated.

• enum spi_inst_t { rcr_inst = 0x00, rbm_inst = 0x3A, wcr_inst = 0x40, wbm_inst = 0x7A, bfs_inst = 0x80, bfc_inst = 0xa0, src_inst = 0xFF }

  SPI instructions.

• enum sfr_bank_t { sfr_bank0 = SFR_BANK0, sfr_bank1 = SFR_BANK1, sfr_bank2 = SFR_BANK2, sfr_bank3 = SFR_BANK3, sfr_common = SFR_COMMON, sfr_bank0 = SFR_BANK0, sfr_bank1 = SFR_BANK1, sfr_bank2 = SFR_BANK2, sfr_bank3 = SFR_BANK3, sfr_common = SFR_COMMON }

  SFR banks.

• enum enc28j60_registers_t { J60_ERDPTL = (SFR_BANK0 | 0x00), J60_ERDPTH = (SFR_BANK0 | 0x01), J60_EWRPTL = (SFR_BANK0 | 0x02), J60_EWRPTH = (SFR_BANK0 | 0x03), J60_ETXSTL = (SFR_BANK0 | 0x04), J60_ETXSTH = (SFR_BANK0 | 0x05), J60_ETXNDL = (SFR_BANK0 | 0x06), J60_ETXNDH = (SFR_BANK0 | 0x07), J60_ERXSTL = (SFR_BANK0 | 0x08), J60_ERXSTH = (SFR_BANK0 | 0x09), J60_ERXNDL = (SFR_BANK0 | 0x0A), J60_ERXNDH = (SFR_BANK0 | 0x0B), J60_ERXRDPTL = (SFR_BANK0 | 0x0C), J60_ERXRDPTH = (SFR_BANK0 | 0x0D), J60_ERXWRPTL = (SFR_BANK0 | 0x0E), J60_ERXWRPTH = (SFR_BANK0 | 0x0F), J60_EDMASTL = (SFR_BANK0 | 0x10), J60_EDMASTH = (SFR_BANK0 | 0x11), J60_EDMANDL = (SFR_BANK0 | 0x12), J60_EDMANDH = (SFR_BANK0 | 0x13), J60_EDMADSTL = (SFR_BANK0 | 0x14), J60_EDMADSTH = (SFR_BANK0 | 0x15), J60_EDMACSL = (SFR_BANK0 | 0x16), J60_EDMACSH = (SFR_BANK0 | 0x17), RSRV_018 = (SFR_BANK0 | 0x18), RSRV_019 = (SFR_BANK0 | 0x19), RSRV_01A = (SFR_BANK0 | 0x1A), J60_EHT0 = (SFR_BANK1 | 0x00), J60_EHT1 = (SFR_BANK1 | 0x01), J60_EHT2 = (SFR_BANK1 | 0x02), J60_EHT3 = (SFR_BANK1 | 0x03), J60_EHT4 = (SFR_BANK1 | 0x04), J60_EHT5 = (SFR_BANK1 | 0x05), J60_EHT6 = (SFR_BANK1 | 0x06), J60_EHT7 = (SFR_BANK1 | 0x07), J60_EPMM0 = (SFR_BANK1 | 0x08), J60_EPMM1 = (SFR_BANK1 | 0x09), J60_EPMM2 = (SFR_BANK1 | 0x0A), J60_EPMM3 = (SFR_BANK1 | 0x0B), J60_EPMM4 = (SFR_BANK1 | 0x0C), J60_EPMM5 = (SFR_BANK1 | 0x0D), J60_EPMM6 = (SFR_BANK1 | 0x0E), J60_EPMM7 = (SFR_BANK1 | 0x0F), J60_EPMCSL = (SFR_BANK1 | 0x10), J60_EPMCSH = (SFR_BANK1 | 0x11), RSRV_112 = (SFR_BANK1 | 0x12), RSRV_113 = (SFR_BANK1 | 0x13), J60_EPMOL = (SFR_BANK1 | 0x14), J60_EPMOH = (SFR_BANK1 | 0x15), RSRV_116 = (SFR_BANK1 | 0x16), RSRV_117 = (SFR_BANK1 | 0x17), J60_ERXFCON = (SFR_BANK1 | 0x18), J60_EPKTCNT = (SFR_BANK1 | 0x19), RSRV_11A = (SFR_BANK1 | 0x1A), J60_MACON1 = (SFR_BANK2 | 0x00), RSRV_201 = (SFR_BANK2 | 0x01), J60_MACON3 = (SFR_BANK2 | 0x02), J60_MACON4 = (SFR_BANK2 | 0x03), J60_MABBIPG = (SFR_BANK2 | 0x04), RSRV_205 = (SFR_BANK2 | 0x05), J60_MAIPGL = (SFR_BANK2 | 0x06), J60_MAIPGH = (SFR_BANK2 | 0x07), J60_MACLCON1 = (SFR_BANK2 | 0x08), J60_MACLCON2 = (SFR_BANK2 | 0x09), J60_MAMXFLL = (SFR_BANK2 | 0x0A), J60_MAMXFLH = (SFR_BANK2 | 0x0B), RSRV_20C = (SFR_BANK2 | 0x0C), RSRV_20D = (SFR_BANK2 | 0x0D), RSRV_20E = (SFR_BANK2 | 0x0E), RSRV_20F = (SFR_BANK2 | 0x0F), RSRV_210 = (SFR_BANK2 | 0x10), RSRV_211 = (SFR_BANK2 | 0x11), J60_MICMD = (SFR_BANK2 | 0x12), RSRV_213 = (SFR_BANK2 | 0x13), J60_MIREGADR = (SFR_BANK2 | 0x14), RSRV_215 = (SFR_BANK2 | 0x15), J60_MIWRL = (SFR_BANK2 | 0x16), J60_MIWRH = (SFR_BANK2 | 0x17), J60_MIRDL = (SFR_BANK2 | 0x18), J60_MIRDH = (SFR_BANK2 | 0x19), RSRV_21A = (SFR_BANK2 | 0x1A), J60_MAADR5 = (SFR_BANK3 | 0x00), J60_MAADR6 = (SFR_BANK3 | 0x01), J60_MAADR3 = (SFR_BANK3 | 0x02), J60_MAADR4 = (SFR_BANK3 | 0x03), J60_MAADR1 = (SFR_BANK3 | 0x04), J60_MAADR2 = (SFR_BANK3 | 0x05), J60_EBSTSD = (SFR_BANK3 | 0x06), J60_EBSTCON = (SFR_BANK3 | 0x07), J60_EBSTCSL = (SFR_BANK3 | 0x08), J60_EBSTCSH = (SFR_BANK3 | 0x09), J60_MISTAT = (SFR_BANK3 | 0x0A), RSRV_30B = (SFR_BANK3 | 0x0B), RSRV_30C = (SFR_BANK3 | 0x0C), RSRV_30D = (SFR_BANK3 | 0x0D), RSRV_30E = (SFR_BANK3 | 0x0E), RSRV_30F = (SFR_BANK3 | 0x0F), RSRV_310 = (SFR_BANK3 | 0x10), RSRV_311 = (SFR_BANK3 | 0x11), J60_EREVID = (SFR_BANK3 | 0x12), RSRV_313 = (SFR_BANK3 | 0x13), RSRV_314 = (SFR_BANK3 | 0x14), J60_ECOCON = (SFR_BANK3 | 0x15), RSRV_316 = (SFR_BANK3 | 0x16), J60_EFLOCON = (SFR_BANK3 | 0x17), J60_EPAUSL = (SFR_BANK3 | 0x18), J60_EPAUSH = (SFR_BANK3 | 0x19), RSRV_31A = (SFR_BANK3 | 0x1A), J60_EIE = (SFR_COMMON | 0x1B), J60_EIR = (SFR_COMMON | 0x1C), J60_ESTAT = (SFR_COMMON | 0x1D), J60_ECON2 = (SFR_COMMON | 0x1E), J60_ECON1 = (SFR_COMMON | 0x1F) }

  ENC28J60 registers.

• enum enc28j60_phy_registers_t { J60_PHCON1 = 0x00, J60_PHSTAT1 = 0x01, J60_PHID1 = 0x02, J60_PHID2 = 0x03, J60_PHCON2 = 0x10, J60_PHSTAT2 = 0x11, J60_PHIE = 0x12, J60_PHIR = 0x13, J60_PHLCON = 0x14 }

  ENC28J60 PHY register addresses.

• phy_error_msg ETH_SendQueued (void)

  Enqueues the latest written packet and starts the transmission of a queued packet.

• phy_error_msg ETH_Shift_Tx_Packets (void)

  Copies the queued packets to the TX Buffer start address using the DMA setup.

• void ETH_PacketListReset (void)

  Resets the Ethernet packet list.

• txPacket_t * ETH_NewPacket (void)

  Allocates a new packet element and links it to the chained list.

• void ETH_RemovePacket (txPacket_t *pPacket)

  Deallocates a packet element and unlinks it from the chained list.

• static uint16_t ETH_ComputeChecksum (uint16_t len, uint16_t seed)

  Calculates the checksum.

• static uint8_t ENC28_Rcr8 (enc28j60_registers_t a)

  Reads one byte from Special Function Register (SFR).

• static uint16_t ENC28_Rcr16 (enc28j60_registers_t a)

  Reads two bytes from SFRs.

• static void ENC28_Wcr8 (enc28j60_registers_t a, uint8_t v)

  Writes one byte to SFRs.

• static void ENC28_Wcr16 (enc28j60_registers_t a, uint16_t v)

  Writes two bytes to SFRs.

• static void ENC28_Bfs (enc28j60_registers_t a, char bits)

  Sets the SFR bit field.

• static void ENC28_Bfc (enc28j60_registers_t a, char bits)

  Clears the SFR bit field.

• static uint16_t ENC28_PhyRead (enc28j60_phy_registers_t a)

  Reads the Physical Layer (PHY) register.

• static void ENC28_PhyWrite (enc28j60_phy_registers_t a, uint16_t d)

  Writes the PHY register.

• static void ENC28_BankSel (enc28j60_registers_t r)

  Selects the bank.

• static void ETH_CloseSPI (void)

  Releases the Serial Peripheral Interface (SPI) bus.

• static void ETH_OpenSPI (void)

  Connects the SPI bus.

• uint8_t Control_Byte

  ENC28J60 Control Byte.

#define ETH_ALLOCATED (0x0001 << 2)

Flag for pool management. Set to either free or allocated.

#define ETH_NCS_HIGH( ) do{ETH_CS_SetHigh();} while(0)

Sets Ethernet Chip Select to high.

#define ETH_NCS_LOW( ) do{ETH_CS_SetLow();} while(0)

Sets Ethernet Chip Select to low.

#define ETH_SPI_READ8( ) SPI1_Host.ByteExchange(0)

Reads the SPI byte.

#define ETH_SPI_WRITE8( a) SPI1_Host.ByteExchange(a)

Writes the SPI byte.

#define ETH_TX_QUEUED (0x0001 << 1)

Packet complete, in queue for transmit.

#define ETH_WRITE_IN_PROGRESS (0x0001 << 0)

Packet write in progress, not ready for transmit.

static void ENC28_BankSel (enc28j60_registers_t r)[static]

Selects the bank.

static void ENC28_Bfc (enc28j60_registers_t a, char bits)[static]

Clears the SFR bit field.

static void ENC28_Bfs (enc28j60_registers_t a, char bits)[static]

Sets the SFR bit field.

static uint16_t ENC28_PhyRead (enc28j60_phy_registers_t a)[static]

Reads the Physical Layer (PHY) register.

static void ENC28_PhyWrite (enc28j60_phy_registers_t a, uint16_t d)[static]

Writes the PHY register.

static uint16_t ENC28_Rcr16 (enc28j60_registers_t a)[static]

Reads two bytes from SFRs.

static uint8_t ENC28_Rcr8 (enc28j60_registers_t a)[static]

Reads one byte from Special Function Register (SFR).

static void ENC28_Wcr16 (enc28j60_registers_t a, uint16_t v)[static]

Writes two bytes to SFRs.

static void ENC28_Wcr8 (enc28j60_registers_t a, uint8_t v)[static]

Writes one byte to SFRs.

static void ETH_CloseSPI (void )[static]

Releases the Serial Peripheral Interface (SPI) bus.

static uint16_t ETH_ComputeChecksum (uint16_t len, uint16_t seed)[static]

Calculates the checksum.

txPacket_t * ETH_NewPacket (void )

Allocates a new packet element and links it to the chained list.

static void ETH_OpenSPI (void )[static]

Connects the SPI bus.

void ETH_PacketListReset (void )

Resets the Ethernet packet list.

void ETH_RemovePacket (txPacket_t * pPacket)

Deallocates a packet element and unlinks it from the chained list.

phy_error_msg ETH_SendQueued (void )

Enqueues the latest written packet and starts the transmission of a queued packet.

phy_error_msg ETH_Shift_Tx_Packets (void )

Copies the queued packets to the TX Buffer start address using the DMA setup.

enum enc28j60_phy_registers_t

ENC28J60 PHY register addresses.

enum enc28j60_registers_t

ENC28J60 registers.

enum sfr_bank_t

SFR banks.

Special Function Register (SFR) Banks.

enum spi_inst_t

SPI instructions.

Control_Byte

ENC28J60 Control Byte.

• union receiveStatusVector_t

  ENC28J60 receive status vector.

• #define ETH_WRITE_IN_PROGRESS (0x0001 << 0)

  Packet write in progress, not ready for transmit.

• #define ETH_TX_QUEUED (0x0001 << 1)

  Packet in queue for transmit.

• #define ETH_ALLOCATED (0x0001 << 2)

  Flag for pool management. Set to either free or allocated.

• #define ETH_NCS_HIGH() do{ETH_CS_SetHigh();} while(0)

  Sets Ethernet Chip Select to high.

• #define ETH_NCS_LOW() do{ETH_CS_SetLow();} while(0)

  Sets Ethernet Chip Select to low.

• #define ETH_READ8() SPI1_Host.ByteExchange(0)

  Reads the Serial Peripheral Interface (SPI) byte.

• #define ETH_WRITE8(a) SPI1_Host.ByteExchange(a)

  Packet write in progress, not ready for transmit.

• #define TXSTART 0x0000ul

  Transmit buffer start.

• #define TXEND 0x15FFul

  Transmit buffer end.

• #define RXSTART 0x1600ul

  Receive buffer start (must be an even memory address).

• #define RXEND (RAMSIZE_ETH - 2)

  Receive buffer end.

• #define PHCON1_PSLEEP 0x0800

  Bit mask for PHY Sleep Enable bit. Physical Layer (PHY) power is down.

• #define PHCON1_PWAKE 0xF7FF

  Bit mask for PHY Wake-Up as a normal operation.

• enum encX24J600_registers_t { XJ600_ETXSTL = (SFR_BANK0 | 0x00), XJ600_ETXLENL = (SFR_BANK0 | 0x02), XJ600_ERXSTL = (SFR_BANK0 | 0x04), XJ600_ERXTAILL = (SFR_BANK0 | 0x06), XJ600_ERXHEADL = (SFR_BANK0 | 0x08), XJ600_EDMASTL = (SFR_BANK0 | 0x0A), XJ600_EDMALENL = (SFR_BANK0 | 0x0C), XJ600_EDMADSTL = (SFR_BANK0 | 0x0E), XJ600_EDMACSL = (SFR_BANK0 | 0x10), XJ600_ETXSTATL = (SFR_BANK0 | 0x12), XJ600_ETXWIREL = (SFR_BANK0 | 0x14), XJ600_EHT1L = (SFR_BANK1 | 0x00), XJ600_EHT2L = (SFR_BANK1 | 0x02), XJ600_EHT3L = (SFR_BANK1 | 0x04), XJ600_EHT4L = (SFR_BANK1 | 0x06), XJ600_EPMM1L = (SFR_BANK1 | 0x08), XJ600_EPMM2L = (SFR_BANK1 | 0x0A), XJ600_EPMM3L = (SFR_BANK1 | 0x0C), XJ600_EPMM4L = (SFR_BANK1 | 0x0E), XJ600_EPMCSL = (SFR_BANK1 | 0x10), XJ600_EPMOL = (SFR_BANK1 | 0x12), XJ600_ERXFCONL = (SFR_BANK1 | 0x14), XJ600_MACON1L = (SFR_BANK2 | 0x00), XJ600_MACON2L = (SFR_BANK2 | 0x02), XJ600_MABBIPGL = (SFR_BANK2 | 0x04), XJ600_MAIPGL = (SFR_BANK2 | 0x06), XJ600_MACLCONL = (SFR_BANK2 | 0x08), XJ600_MAMXFLL = (SFR_BANK2 | 0x0A), XJ600_MICMDL = (SFR_BANK2 | 0x12), XJ600_MIREGADRL = (SFR_BANK2 | 0x14), XJ600_MAADR3L = (SFR_BANK3 | 0x00), XJ600_MAADR3H = (SFR_BANK3 | 0x01), XJ600_MAADR2L = (SFR_BANK3 | 0x02), XJ600_MAADR2H = (SFR_BANK3 | 0x03), XJ600_MAADR1L = (SFR_BANK3 | 0x04), XJ600_MAADR1H = (SFR_BANK3 | 0x05), XJ600_MIWRL = (SFR_BANK3 | 0x06), XJ600_MIRDL = (SFR_BANK3 | 0x08), XJ600_MISTATL = (SFR_BANK3 | 0x0A), XJ600_EPAUSL = (SFR_BANK3 | 0x0C), XJ600_ECON2L = (SFR_BANK3 | 0x0E), XJ600_ERXWML = (SFR_BANK3 | 0x10), XJ600_EIEL = (SFR_BANK3 | 0x12), XJ600_EIDLEDL = (SFR_BANK3 | 0x14), XJ600_EGPDATAL = (UNBANKED | 0x00), XJ600_ERXDATAL = (UNBANKED | 0x02), XJ600_EUDADATAL = (UNBANKED | 0x04), XJ600_EGPRDPTL = (UNBANKED | 0x06), XJ600_EGPWRPTL = (UNBANKED | 0x08), XJ600_ERXRDPTL = (UNBANKED | 0x0A), XJ600_ERXWRPTL = (UNBANKED | 0x0C), XJ600_EUDARDPTL = (UNBANKED | 0x0E), XJ600_EUDAWRPTL = (UNBANKED | 0x10), XJ600_EUDASTL = (SFR_COMMON | 0x16), XJ600_EUDANDL = (SFR_COMMON | 0x18), XJ600_ESTATL = (SFR_COMMON | 0x1A), XJ600_EIRL = (SFR_COMMON | 0x1C), XJ600_ECON1L = (SFR_COMMON | 0x1E) }

  SFR addresses for the ENCx24J600 SPI mode.

• enum encX24J600_1_byte_instructions_t { b0sel_inst = 0b11000000, b1sel_inst = 0b11000010, b2sel_inst = 0b11000100, b3sel_inst = 0b11000110, setethrst_inst = 0b11001010, fcdisable_inst = 0b11100000, fcsingle_inst = 0b11100010, fcmultiple_inst = 0b11100100, fcclear_inst = 0b11100110, setpktdec_inst = 0b11001100, dmastop_inst = 0b11010010, dmacksum_inst = 0b11011000, dmacksums_inst = 0b11011010, dmacopy_inst = 0b11011100, dmacopys_inst = 0b11011110, settxrts_inst = 0b11010100, enablerx_inst = 0b11101000, disablerx_inst = 0b11101010, seteie_inst = 0b11101100, clreie_inst = 0b11101110 }

  SPI single byte instructions.

• enum encX24J600_2_byte_instructions_t { rbsel_inst = 0b11001000 }

  SPI two byte instructions.

• enum encX24J600_3_byte_instructions_t { rgprdpt_inst = 0b01100010, rrxrdpt_inst = 0b01100110, rgpwrpt_inst = 0b01101110, rrxwrpt_inst = 0b01110010, rudawrpt_inst = 0b01110110, wgprdpt_inst = 0b01100000, wrxrdpt_inst = 0b01100100, wgpwrpt_inst = 0b01101100, wrxwrpt_inst = 0b01110000, wudawrpt_inst = 0b01110100 }

  SPI three byte instructions.

• enum encX24J600_N_byte_instructions_t { rcr_inst = 0b00000000, wcr_inst = 0b01000000, bfs_inst = 0b10000000, bfc_inst = 0b10100000, rcru_inst = 0b00100000, wcru_inst = 0b00100010, bfsu_inst = 0b00100100, bfcu_inst = 0b00100110, rgpdata_inst = 0b00101000, rrxdata_inst = 0b00101100, rudadata_inst = 0b00110000, wgpdata_inst = 0b00101010, wrxdata_inst = 0b00101110, wudadata_inst = 0b00110010 }

  SPI N byte instructions.

• enum encX24J600_phy_registers_t { PHCON1 = 0x00, PHSTAT1 = 0x01, PHANA = 0x04, PHANLPA = 0x05, PHANE = 0x06, PHCON2 = 0x11, PHSTAT2 = 0x1B, PHSTAT3 = 0x1F }

  ENCX24J600 PHY registers.

• phy_error_msg ETH_SendQueued (void)

  Enqueues the latest written packet and starts the transmission of a queued packet.

• phy_error_msg ETH_Shift_Tx_Packets (void)

  Copies all the queued packets to the TX Buffer start address using the DMA setup.

• void ETH_PacketListReset (void)

  Resets the Ethernet packet list.

• txPacket_t * ETH_NewPacket (void)

  Allocates a new packet element and links it to the chained list.

• void ETH_RemovePacket (txPacket_t *pPacket)

  Deallocates a packet element and unlinks it from the chained list.

• static uint16_t ETH_DMAComputeChecksum (uint16_t rxPtr, uint16_t len, uint16_t seed)

  Calculates the checksum.

• static void ETH_CloseSPI (void)

  Releases the Serial Peripheral Interface (SPI) bus.

• static void ETH_OpenSPI (void)

  Connects the SPI bus.

• static void waitForDMA (void)

  Waits for the DMA.

• static uint32_t ETH_readLinkStatus (void)

  Checks for the link status.

• static void ENCx24_BankselSPI (encX24J600_registers_t a)

  Selects the SPI bank.

• uint16_t ENCx24_Read (encX24J600_registers_t a)

  Reads from Special Function Register (SFR).

• uint8_t ETH_EdataRead (encX24J600_registers_t a)

  Reads the 8-bit data from the ENCx24J600 register (work around for Errata).

• void ENCx24_Write (encX24J600_registers_t a, uint16_t data)

  Writes to SFRs.

• void ENCx24_BFS (encX24J600_registers_t a, uint16_t bitMask)

  Sets the SFR bit field.

• void ENCx24_BFC (encX24J600_registers_t a, uint16_t bitMask)

  Clears the SFR bit field.

• uint16_t ENCx24_PhyRead (encX24J600_phy_registers_t a)

  Reads the PHY register.

• void ENCx24_PHYWrite (encX24J600_phy_registers_t a, uint16_t data)

  Writes the PHY register.

• uint8_t ETH_MACRead8 (encX24J600_registers_t a)

  Reads the 8-bit MAC-related data from ENCx24J600 registers.

• void ETH_MACWrite8 (encX24J600_registers_t a, uint8_t data)

  Writes the 8-bit MAC-related data to ENCx24J600 registers.

• void ETH_SetPktDec (void)

  Decrements packet count.

• void ETH_SetRXptr (uint16_t address)

  RX packet read pointer.

• void ETH_Set_TXRTS (void)

  Packet transmission request.

#define ETH_ALLOCATED (0x0001 << 2)

Flag for pool management. Set to either free or allocated.

#define ETH_NCS_HIGH( ) do{ETH_CS_SetHigh();} while(0)

Sets Ethernet Chip Select to high.

#define ETH_NCS_LOW( ) do{ETH_CS_SetLow();} while(0)

Sets Ethernet Chip Select to low.

#define ETH_READ8( ) SPI1_Host.ByteExchange(0)

Reads the Serial Peripheral Interface (SPI) byte.

#define ETH_TX_QUEUED (0x0001 << 1)

Packet in queue for transmit.

#define ETH_WRITE8( a) SPI1_Host.ByteExchange(a)

Packet write in progress, not ready for transmit.

#define ETH_WRITE_IN_PROGRESS (0x0001 << 0)

Packet write in progress, not ready for transmit.

#define PHCON1_PSLEEP 0x0800

Bit mask for PHY Sleep Enable bit. Physical Layer (PHY) power is down.

#define PHCON1_PWAKE 0xF7FF

Bit mask for PHY Wake-Up as a normal operation.

#define RXEND (RAMSIZE_ETH - 2)

Receive buffer end.

#define RXSTART 0x1600ul

Receive buffer start (must be an even memory address).

#define TXEND 0x15FFul

Transmit buffer end.

#define TXSTART 0x0000ul

Transmit buffer start.

static void ENCx24_BankselSPI (encX24J600_registers_t a)[static]

Selects the SPI bank.

void ENCx24_BFC (encX24J600_registers_t a, uint16_t bitMask)

Clears the SFR bit field.

void ENCx24_BFS (encX24J600_registers_t a, uint16_t bitMask)

Sets the SFR bit field.

uint16_t ENCx24_PhyRead (encX24J600_phy_registers_t a)

Reads the PHY register.

void ENCx24_PHYWrite (encX24J600_phy_registers_t a, uint16_t data)

Writes the PHY register.

uint16_t ENCx24_Read (encX24J600_registers_t a)

Reads from Special Function Register (SFR).

void ENCx24_Write (encX24J600_registers_t a, uint16_t data)

Writes to SFRs.

static void ETH_CloseSPI (void )[static]

Releases the Serial Peripheral Interface (SPI) bus.

static uint16_t ETH_DMAComputeChecksum (uint16_t rxPtr, uint16_t len, uint16_t seed)[static]

Calculates the checksum.

uint8_t ETH_EdataRead (encX24J600_registers_t a)

Reads the 8-bit data from the ENCx24J600 register (work around for Errata).

uint8_t ETH_MACRead8 (encX24J600_registers_t a)

Reads the 8-bit MAC-related data from ENCx24J600 registers.

void ETH_MACWrite8 (encX24J600_registers_t a, uint8_t data)

Writes the 8-bit MAC-related data to ENCx24J600 registers.

txPacket_t* ETH_NewPacket (void )

Allocates a new packet element and links it to the chained list.

static void ETH_OpenSPI (void )[static]

Connects the SPI bus.

void ETH_PacketListReset (void )

Resets the Ethernet packet list.

inline static uint32_t ETH_readLinkStatus (void )

Checks for the link status.

void ETH_RemovePacket (txPacket_t * pPacket)

Deallocates a packet element and unlinks it from the chained list.

phy_error_msg ETH_SendQueued (void )

Enqueues the latest written packet and starts the transmission of a queued packet.

void ETH_Set_TXRTS (void )

Packet transmission request.

void ETH_SetPktDec (void )

Decrements packet count.

void ETH_SetRXptr (uint16_t address)

RX packet read pointer.

phy_error_msg ETH_Shift_Tx_Packets (void )

Copies all the queued packets to the TX Buffer start address using the DMA setup.

inline static void waitForDMA (void )

Waits for the DMA.

enum encX24J600_1_byte_instructions_t

SPI single byte instructions.

enum encX24J600_2_byte_instructions_t

SPI two byte instructions.

enum encX24J600_3_byte_instructions_t

SPI three byte instructions.

enum encX24J600_N_byte_instructions_t

SPI N byte instructions.

enum encX24J600_phy_registers_t

ENCX24J600 PHY registers.

enum encX24J600_registers_t

SFR addresses for the ENCx24J600 SPI mode.

• union mac48Address_t

  MAC Address (48-bits).

• union mac64Address_t

  MAC Address (64-bits).

• enum phy_error_msg { PHY_ERROR = 0, PHY_SUCCESS, PHY_LINK_NOT_FOUND, PHY_BUFFER_BUSY, PHY_TX_LOGIC_NOT_IDLE, PHY_TX_QUEUED, PHY_DMA_TIMEOUT }

  PHY status/errors.

• void ETH_Init (void)

  Sets up the Ethernet and starts the execution. Initializes the TX/RX buffer, the MAC and the PHY.

• void ETH_EventHandler (void)

  Manages the MAC events. Can be used for polling or for new events in Interrupt Service Routine (ISR).

• void ETH_NextPacketUpdate (void)

  Updates the pointers for the next available RX packets. Retrieves information about the last received packet and the address of the next ones.

• void ETH_ResetReceiver (void)

  Resets the receiver buffer.

• void ETH_SendSystemReset (void)

  Resets the system software.

• const mac48Address_t * MAC_getAddress (void)

  Returns the MAC address of type mac48Address_t.

• uint16_t ETH_ReadBlock (void *buffer, uint16_t length)

  Reads a block of data from the RX buffer MAC.

• uint8_t ETH_Read8 (void)

  Reads one byte of data from the RX buffer MAC.

• uint16_t ETH_Read16 (void)

  Reads two bytes of data from the RX buffer and returns them in host order.

• uint32_t ETH_Read24 (void)

  Reads three bytes of data from the RX buffer and returns them in host order.

• uint32_t ETH_Read32 (void)

  Reads four bytes of data from the RX buffer and returns them in host order.

• void ETH_Dump (uint16_t length)

  Drops the N bytes from a packet list when the data is lost. Clears a number of bytes (length) from the RX buffer.

• void ETH_Flush (void)

  Drops the rest of this packet and release the buffer. Clears all bytes from the RX buffer.

• uint16_t ETH_GetFreeTxBufferSize (void)

  Returns the available space size in the Ethernet TX buffer.

• phy_error_msg ETH_WriteStart (const mac48Address_t *dest_mac, uint16_t type)

  Starts a packet if the Ethernet transmitter is idle.

• uint16_t ETH_WriteString (const char *string)

  Writes a string of data into the MAC.

• uint16_t ETH_WriteBlock (const char *data, uint16_t length)

  Writes a block of data into the TX buffer MAC.

• void ETH_Write8 (uint8_t data)

  Writes one byte of data into the TX buffer MAC.

• void ETH_Write16 (uint16_t data)

  Writes two bytes into the TX buffer MAC in Network order.

• void ETH_Write24 (uint32_t data)

  Writes three bytes into the TX buffer MAC in Network order.

• void ETH_Write32 (uint32_t data)

  Writes four bytes into the TX buffer MAC in Network order.

• void ETH_Insert (char *data, uint16_t len, uint16_t offset)

  Inserts N data bytes into a specific offset in the TX buffer/packet.

• phy_error_msg ETH_Copy (uint16_t len)

  Copies N bytes from the saved read location (RX buffer) into the current TX location (TX buffer) using the DMA set up. This is used for ICMP ECHO to eliminate the need to extract the arbitrary payload.

• phy_error_msg ETH_Send (void)

  Sends the TX packet. Starts the transmission of packet or queues the packet that has been created.

• uint16_t ETH_TxComputeChecksum (uint16_t position, uint16_t length, uint16_t seed)

  Calculates the hardware checksum of length bytes starting with the position.

• uint16_t ETH_RxComputeChecksum (uint16_t len, uint16_t seed)

  Calculates the RX software checksum.

• void ETH_GetMAC (uint8_t *macAddr)

  Reads the MAC address.

• void ETH_SetMAC (uint8_t *macAddr)

  Sets the MAC address.

• uint16_t ETH_GetWritePtr (void)

  Returns the value of the write pointer.

• void ETH_SaveRDPT (void)

  Saves the receive pointer for copy.

• void ETH_ResetReadPtr (void)

  Resets the receive pointer to the Init.

• uint16_t ETH_GetReadPtr (void)

  Returns the value of the read pointer.

• void ETH_SetReadPtr (uint16_t rdptr)

  Sets the read pointer to a specific address.

• uint16_t ETH_GetStatusVectorByteCount (void)

  Returns the Status Vector's byte count.

• void ETH_SetStatusVectorByteCount (uint16_t bc)

  Sets the Status Vector's byte count.

• void ETH_ResetByteCount (void)

  Resets the driver's byte count.

• uint16_t ETH_GetByteCount (void)

  Returns the the driver's byte count.

• uint16_t ETH_ReadSavedWRPT (void)

  Returns the saved write pointer.

• void ETH_SaveWRPT (void)

  Saves the write pointer for copy.

• void ETH_SetRxByteCount (uint16_t count)

  Sets the receiver's byte count.

• uint16_t ETH_GetRxByteCount (void)

  Returns the receiver's byte count.

• bool ETH_CheckLinkUp (void)

  Checks for the link.

• void ETH_TxReset (void)

  Resets the transmitter.

• void ETH_MoveBackReadPtr (uint16_t offset)

  Moves back the read pointer.

bool ETH_CheckLinkUp (void )

Checks for the link.

phy_error_msg ETH_Copy (uint16_t len)

Copies N bytes from the saved read location (RX buffer) into the current TX location (TX buffer) using the DMA set up. This is used for ICMP ECHO to eliminate the need to extract the arbitrary payload.

void ETH_Dump (uint16_t length)

Drops the N bytes from a packet list when the data is lost. Clears a number of bytes (length) from the RX buffer.

void ETH_EventHandler (void )

Manages the MAC events. Can be used for polling or for new events in Interrupt Service Routine (ISR).

void ETH_Flush (void )

Drops the rest of this packet and release the buffer. Clears all bytes from the RX buffer.

uint16_t ETH_GetByteCount (void )

Returns the the driver's byte count.

uint16_t ETH_GetFreeTxBufferSize (void )

Returns the available space size in the Ethernet TX buffer.

void ETH_GetMAC (uint8_t * macAddr)

Reads the MAC address.

uint16_t ETH_GetReadPtr (void )

Returns the value of the read pointer.

uint16_t ETH_GetRxByteCount (void )

Returns the receiver's byte count.

uint16_t ETH_GetStatusVectorByteCount (void )

Returns the Status Vector's byte count.

uint16_t ETH_GetWritePtr (void )

Returns the value of the write pointer.

void ETH_Init (void )

Sets up the Ethernet and starts the execution. Initializes the TX/RX buffer, the MAC and the PHY.

void ETH_Insert (char * data, uint16_t len, uint16_t offset)

Inserts N data bytes into a specific offset in the TX buffer/packet.

void ETH_MoveBackReadPtr (uint16_t offset)

Moves back the read pointer.

void ETH_NextPacketUpdate (void )

Updates the pointers for the next available RX packets. Retrieves information about the last received packet and the address of the next ones.

uint16_t ETH_Read16 (void )

Reads two bytes of data from the RX buffer and returns them in host order.

uint32_t ETH_Read24 (void )

Reads three bytes of data from the RX buffer and returns them in host order.

uint32_t ETH_Read32 (void )

Reads four bytes of data from the RX buffer and returns them in host order.

uint8_t ETH_Read8 (void )

Reads one byte of data from the RX buffer MAC.

uint16_t ETH_ReadBlock (void * buffer, uint16_t length)

Reads a block of data from the RX buffer MAC.

uint16_t ETH_ReadSavedWRPT (void )

Returns the saved write pointer.

void ETH_ResetByteCount (void )

Resets the driver's byte count.

void ETH_ResetReadPtr (void )

Resets the receive pointer to the Init.

void ETH_ResetReceiver (void )

Resets the receiver buffer.

uint16_t ETH_RxComputeChecksum (uint16_t len, uint16_t seed)

Calculates the RX software checksum.

void ETH_SaveRDPT (void )

Saves the receive pointer for copy.

void ETH_SaveWRPT (void )

Saves the write pointer for copy.

phy_error_msg ETH_Send (void )

Sends the TX packet. Starts the transmission of packet or queues the packet that has been created.

void ETH_SendSystemReset (void )

Resets the system software.

void ETH_SetMAC (uint8_t * macAddr)

Sets the MAC address.

void ETH_SetReadPtr (uint16_t rdptr)

Sets the read pointer to a specific address.

void ETH_SetRxByteCount (uint16_t count)

Sets the receiver's byte count.

void ETH_SetStatusVectorByteCount (uint16_t bc)

Sets the Status Vector's byte count.

uint16_t ETH_TxComputeChecksum (uint16_t position, uint16_t length, uint16_t seed)

Calculates the hardware checksum of length bytes starting with the position.

void ETH_TxReset (void )

Resets the transmitter.

void ETH_Write16 (uint16_t data)

Writes two bytes into the TX buffer MAC in Network order.

void ETH_Write24 (uint32_t data)

Writes three bytes into the TX buffer MAC in Network order.

void ETH_Write32 (uint32_t data)

Writes four bytes into the TX buffer MAC in Network order.

void ETH_Write8 (uint8_t data)

Writes one byte of data into the TX buffer MAC.

uint16_t ETH_WriteBlock (const char * data, uint16_t length)

Writes a block of data into the TX buffer MAC.

phy_error_msg ETH_WriteStart (const mac48Address_t * dest_mac, uint16_t type)

Starts a packet if the Ethernet transmitter is idle.

uint16_t ETH_WriteString (const char * string)

Writes a string of data into the MAC.

const mac48Address_t* MAC_getAddress (void )

Returns the MAC address of type mac48Address_t.

enum phy_error_msg

PHY status/errors.

• char val

• struct {

  • unsigned RXERIF: 1

  • unsigned TXERIF: 1

  • unsigned __pad0__: 1

  • unsigned TXIF: 1

  • unsigned LINKIF: 1

  • unsigned DMAIF: 1

  • unsigned PKTIF: 1

  • unsigned __pad1__: 1

• };

struct { ... }

unsigned __pad0__

unsigned __pad1__

unsigned DMAIF

DMA Interrupt Flag bit

unsigned LINKIF

Link Change Interrupt Flag bit

unsigned PKTIF

Receive Packet Pending Interrupt Flag bit

unsigned RXERIF

Receive Error Interrupt Flag bit

unsigned TXERIF

Transmit Error Interrupt Flag bit

unsigned TXIF

Transmit Interrupt Flag bit

char val

unsigned __pad0__

unsigned bufferBusy

unsigned error

unsigned idle

unsigned linkChange

unsigned pktReady

uint16_t saveRDPT

uint16_t saveWRPT

unsigned up

• uint8_t mac_array [6]

• struct {

  • uint8_t byte1

  • uint8_t byte2

  • uint8_t byte3

  • uint8_t byte4

  • uint8_t byte5

  • uint8_t byte6

• } s

uint8_t byte1

uint8_t byte2

uint8_t byte3

uint8_t byte4

uint8_t byte5

uint8_t byte6

uint8_t mac_array[6]

struct { ... } s

• uint8_t mac_array [8]

• struct {

  • uint8_t byte1

  • uint8_t byte2

  • uint8_t byte3

  • uint8_t byte4

  • uint8_t byte5

  • uint8_t byte6

  • uint8_t byte7

  • uint8_t byte8

• } s

uint8_t byte1

uint8_t byte2

uint8_t byte3

uint8_t byte4

uint8_t byte5

uint8_t byte6

uint8_t byte7

uint8_t byte8

uint8_t mac_array[8]

struct { ... } s

• unsigned int val

• struct {

  • unsigned __pad0__: 5

  • unsigned PLRITY: 1

  • unsigned __pad1__: 3

  • unsigned DPXSTAT: 1

  • unsigned LSTAT: 1

  • unsigned COLSTAT: 1

  • unsigned RXSTAT: 1

  • unsigned TXSTAT: 1

  • unsigned __pad2__: 2

• };

struct { ... }

unsigned __pad0__

unsigned __pad1__

unsigned __pad2__

unsigned COLSTAT

PHY Collision Status bit

unsigned DPXSTAT

PHY Duplex Status bit

unsigned LSTAT

PHY Link Status bit (non-latching)

unsigned PLRITY

Polarity Status bit

unsigned RXSTAT

PHY Receive Status bit

unsigned TXSTAT

PHY Transmit Status bit

unsigned int val

• uint8_t v [4]

• struct {

  • uint16_t byteCount

  • unsigned long_drop_event: 1

  • unsigned __pad0__: 1

  • unsigned excessCarrierEvent: 1

  • unsigned __pad1__: 1

  • unsigned crcError: 1

  • unsigned lengthCheckError: 1

  • unsigned lengthLongError: 1

  • unsigned rxOK: 1

  • unsigned rxMulticast: 1

  • unsigned rxBroadcast: 1

  • unsigned dribbleNibble: 1

  • unsigned controlFrame: 1

  • unsigned pauseControlFrame: 1

  • unsigned unknownContrlFrame: 1

  • unsigned vlanTagPresent: 1

  • unsigned zero: 1

• };

• struct {

  • uint16_t byteCount

  • unsigned PreviouslyIgnored: 1

  • unsigned RXDCPreviouslySeen: 1

  • unsigned CarrierPreviouslySeen: 1

  • unsigned CodeViolation: 1

  • unsigned CRCError: 1

  • unsigned LengthCheckError: 1

  • unsigned LengthOutOfRange: 1

  • unsigned ReceiveOk: 1

  • unsigned Multicast: 1

  • unsigned Broadcast: 1

  • unsigned DribbleNibble: 1

  • unsigned ControlFrame: 1

  • unsigned PauseControlFrame: 1

  • unsigned UnsupportedOpcode: 1

  • unsigned VLANType: 1

  • unsigned RuntMatch: 1

  • unsigned filler: 1

  • unsigned HashMatch: 1

  • unsigned MagicPacketMatch: 1

  • unsigned PatternMatch: 1

  • unsigned UnicastMatch: 1

  • unsigned BroadcastMatch: 1

  • unsigned MulticastMatch: 1

  • unsigned ZeroH: 1

  • unsigned char Zero: 8

• };

struct { ... }

struct { ... }

unsigned __pad0__

unsigned __pad1__

unsigned Broadcast

Receive Broadcast Packet

unsigned BroadcastMatch

Broadcast Filter Match

uint16_t byteCount

Received Byte Count

unsigned CarrierPreviouslySeen

Carrier Event Previously Seen

unsigned CodeViolation

Code Violation

unsigned ControlFrame

Receive Control Frame

unsigned controlFrame

Receive Control Frame

unsigned CRCError

CRC Error

unsigned crcError

CRC Error

unsigned DribbleNibble

Dribble Nibble

unsigned dribbleNibble

Dribble Nibble

unsigned excessCarrierEvent

Carrier Event Previously Seen

unsigned filler

Not-Me Filter Match

unsigned HashMatch

Hash Filter Match

unsigned LengthCheckError

Length Check Error

unsigned lengthCheckError

Length Check Error

unsigned lengthLongError

Length Out of Range

unsigned LengthOutOfRange

Length Out of Range

unsigned long_drop_event

Long Event/Drop Event

unsigned MagicPacketMatch

Magic Packet(TM) Filter Match

unsigned Multicast

Receive Multicast Packet

unsigned MulticastMatch

Multicast Filter Match

unsigned PatternMatch

Pattern Match Filter Match

unsigned PauseControlFrame

Receive Pause Control Frame

unsigned pauseControlFrame

Receive Pause Control Frame

unsigned PreviouslyIgnored

Packet Previously Ignored

unsigned ReceiveOk

Received Ok

unsigned RuntMatch

Runt Filter Match

unsigned rxBroadcast

Receive Broadcast Packet

unsigned RXDCPreviouslySeen

RXDC Previously Seen

unsigned rxMulticast

Receive Multicast Packet

unsigned rxOK

Received Ok

unsigned UnicastMatch

Unicast Filter Match

unsigned unknownContrlFrame

Receive Unknown Opcode

unsigned UnsupportedOpcode

Receive Unknown Opcode

uint8_t v

unsigned vlanTagPresent

Receive VLAN Type Detected

unsigned VLANType

Receive VLAN Type Detected

unsigned char Zero

unsigned zero

Zero

unsigned ZeroH

Zero

uint16_t flags

void* nextPacket

uint16_t packetEnd

uint16_t packetStart

void* prevPacket

#define BROADCAST_MAC {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}

#define CheckBit( bitField, bitMask) (bool)(bitField & bitMask)

#define ClearBit( bitField, bitMask) do{ bitField = bitField & (~bitMask); } while(0)

#define MAC_ADDRESS {0x02, 0x00, 0x00, 0x00, 0x00, 0x01}

#define MAX_TX_PACKET_SIZE (1518)

#define MAX_TX_PACKETS (20)

#define MIN_TX_PACKET (MIN_TX_PACKET_SIZE + TX_STATUS_VECTOR_SIZE)

#define MIN_TX_PACKET_SIZE (64)

#define RAMSIZE_ETH (0x1FFF)

#define RXEND (TXSTART - 2)

#define RXSTART (0)

#define SetBit( bitField, bitMask) do{ bitField = bitField | bitMask; } while(0)

#define TX_BUFFER_MID ((TXSTART) + ((TX_BUFFER_SIZE) >> 1))

#define TX_BUFFER_SIZE ((MAX_TX_PACKET_SIZE + TX_STATUS_VECTOR_SIZE) << 1)

#define TX_STATUS_VECTOR_SIZE (7)

#define TXEND (RAMSIZE_ETH)

#define TXSTART (RAMSIZE_ETH - TX_BUFFER_SIZE)

const mac48Address_t broadcastMAC = {BROADCAST_MAC}

const mac48Address_t* eth_MAC

volatile ethernetDriver_t ethData

uint8_t ethListSize

sfr_bank_t lastBank

mac48Address_t macAddress = {MAC_ADDRESS}

uint16_t nextPacketPointer[static]

txPacket_t* pHead[static]

txPacket_t* pTail[static]

receiveStatusVector_t rxPacketStatusVector[static]

txPacket_t txData[MAX_TX_PACKETS][static]

uint16_t TXPacketSize

#define BANK_MASK 0xE0

#define byteReverse24( a) (((((uint32_t)a & (uint32_t)0x00FF00) >> 8) | (((uint32_t)a & (uint32_t)0x0000FF) << 8)) << 8 | (uint32_t)a >> 0x10)

#define byteReverse32( a)

Value:

((((uint32_t)a & (uint32_t)0xff000000) >> 24) | \
                          (((uint32_t)a & (uint32_t)0x00ff0000) >> 8)  | \
                          (((uint32_t)a & (uint32_t)0x0000ff00) << 8)  | \
                          (((uint32_t)a & (uint32_t)0x000000ff) << 24))

#define byteSwap16( a) ((((uint16_t)a & (uint16_t)0xFF00) >> 8) | (((uint16_t)a & (uint16_t)0x00FF) << 8))

#define convert_hton24( a) byteReverse24(a)

#define htonl( a) byteReverse32(a)

#define htons( a) byteSwap16(a)

#define ntohl( a) byteReverse32(a)

#define ntohs( a) byteSwap16(a)

#define SFR_BANK0 0x00

#define SFR_BANK1 0x40

#define SFR_BANK2 0x80

#define SFR_BANK3 0xC0

#define SFR_COMMON 0xE0

#define SFR_MASK 0x1F

#define BROADCAST_MAC {0xff,0xff,0xff,0xff,0xff,0xff}

#define CheckBit( bitField, bitMask) (bool)(bitField & bitMask)

#define ClearBit( bitField, bitMask) do{bitField = bitField & (~bitMask); } while(0)

#define MAC_ADDRESS {0x02, 0x00, 0x00, 0x00, 0x00, 0x01}

#define MAX_TX_PACKET_SIZE (1518)

#define MAX_TX_PACKETS (20)

#define MIN_TX_PACKET (MIN_TX_PACKET_SIZE)

#define MIN_TX_PACKET_SIZE (64)

#define SetBit( bitField, bitMask) do{bitField = bitField | bitMask; } while(0)

#define TX_BUFFER_MID ((TXSTART + TXEND) >> 1)

#define TX_BUFFER_SIZE (TXEND - TXSTART)

const mac48Address_t broadcastMAC = {BROADCAST_MAC}

volatile ethernetDriver_t ethData

uint8_t ethListSize

mac48Address_t ethMAC

mac48Address_t macAddress = {MAC_ADDRESS}

uint16_t nextPacketPointer[static]

txPacket_t* pHead[static]

txPacket_t* pTail[static]

txPacket_t txData[MAX_TX_PACKETS][static]

sfr_bank_t last_bank

receiveStatusVector_t rxPacketStatusVector = {{0, 0, 0, 0, 0, 0}}

uint16_t TXPacketSize

#define BANK_MASK 0xE0

#define byteReverse24( a) (((((uint32_t)a & (uint32_t)0x00FF00) >> 8) | (((uint32_t)a & (uint32_t)0x0000FF) << 8)) << 8 | (uint32_t)a >> 0x10)

#define byteReverse32( a)

Value:

((((uint32_t)a & (uint32_t)0xff000000) >> 24) | \
                          (((uint32_t)a & (uint32_t)0x00ff0000) >> 8)  | \
                          (((uint32_t)a & (uint32_t)0x0000ff00) << 8)  | \
                          (((uint32_t)a & (uint32_t)0x000000ff) << 24))

#define byteSwap16( a) ((((uint16_t)a & (uint16_t)0xFF00) >> 8) | (((uint16_t)a & (uint16_t)0x00FF) << 8))

#define convert_hton24( a) byteReverse24(a)

#define htonl( a) byteReverse32(a)

#define htons( a) byteSwap16(a)

#define ntohl( a) byteReverse32(a)

#define ntohs( a) byteSwap16(a)

#define SFR_BANK0 0x00

#define SFR_BANK1 0x20

#define SFR_BANK2 0x40

#define SFR_BANK3 0x60

#define SFR_COMMON 0xE0

#define SFR_MASK 0x1F

#define UNBANKED 0X80

enum sfr_bank_t

receiveStatusVector_t rxPacketStatusVector

uint16_t TXPacketSize

#define ECON1_AESST 0x0800

#define ECON1_DMACPY 0x0010

#define ECON1_DMACSSD 0x0008

#define ECON1_DMANOCS 0x0004

#define ECON1_DMAST 0x0020

#define ECON1_HASHEN 0x4000

#define ECON1_HASHLST 0x1000

#define ECON1_HASHOP 0x2000

#define ECON1_MODEXST 0x8000

#define ECON1_PKTDEC 0x0100

#define ECON1_RXEN 0x0001

#define ECON1_TXRTS 0x0002

#define ECON2_AUTOFC 0x0080

#define ECON2_ETHEN 0x8000

#define ECON2_ETHRST 0x0010

#define ECON2_RXRST 0x0020

#define ECON2_STRCH 0x4000

#define EIR_CRYPTEN 0x8000

#define EIR_LINKIF 0x0800

#define EIR_PCFULIF 0x0001

#define EIR_PKTIF 0x0040

#define EIR_RXABTIF 0x0002

#define EIR_TXIF 0x0008

#define ESTAT_CLKRDY 0x1000

#define ESTAT_PHYDPX 0x0400

#define ESTAT_PHYLINK 0x0100

#define ESTAT_PHYRDY 0x0200

#define ESTAT_PKTCNT 0x00FF

#define ESTAT_RSTDONE 0x0800

#define ESTAT_RXBUSY 0x2000

#define ETH_HEADER_SIZE 14

#define IP_PROTOCOL_POS 23

#define MACON2_FULDPX_OFF 0xFFFE

#define MACON2_FULDPX_ON 0x0001

#define RAMSIZE_ETH 0x6000ul