2.1 Code Example - Audio PLL

The following code snippet specifies the steps to configure and enable the Audio PLL module.

Requirements:

f_ref = 12 MHz

f_audiopllck = 12.288 MHz

f_audiopinclk = 12.288 MHz

620 MHz ≤ f_{audiocoreclock} ≤ 700 MHz

The values for ND, FRACR, QDPMC, QDAUDIO and DIV that meet the above requirements can be calculated either by a trial-and-error approach or by using code routines. For simplicity, a trial-and-error approach is used, resulting in the following values: ND = 54, FRACR = 1241514, QDPMC = 53, QDAUDIO = 27 and DIV = 2, all of which meet the specified requirements. Procedural calculation routines are available as part of the SAMA5D2 Linux BSP. Specifically, the Linux clock driver available at https://github.com/linux4sam/linux-at91/tree/master/drivers/clk/at91 can be used as a reference.

With the above-calculated Audio PLL parameters, the audio core clock is as follows:

f_{audiocoreclock} = 12000000 * (54 + 1 + (1241514 / 2^22)) = 663.552 MHz. The Audio PLL clock fed to the PMC will be:

f_audiopllck = 663.552 MHz / (53 + 1) = 12.288 MHz. The audio pin clock fed to the CLK_AUDIO pin will be:

f_audiopinclk = 663.552 MHz / (2 * 27) = 12.288 MHz.

Code Snippet:


/* Disable Audio PLL */
PMC->PMC_AUDIO_PLL0 = 0;

/* Set Audio PLL in active state */
PMC->PMC_AUDIO_PLL0 = PMC_AUDIO_PLL0_RESETN;

/* Set Audio PLL parameters – Numbers calculated in trial and error for above spec */
PMC->PMC_AUDIO_PLL0 |= PMC_AUDIO_PLL0_ND(54) | PMC_AUDIO_PLL0_QDPMC(53);

PMC->PMC_AUDIO_PLL1 = PMC_AUDIO_PLL1_FRACR(1241514) 
                       | PMC_AUDIO_PLL1_DIV(2) 
                       | PMC_AUDIO_PLL1_QDAUDIO(27);

/* Enable Audio PLL */
PMC->PMC_AUDIO_PLL0 |= PMC_AUDIO_PLL0_PLLEN | PMC_AUDIO_PLL0_PADEN | PMC_AUDIO_PLL0_PMCEN;

/* Wait for startup time until PLL is stabilized */
delay_us(100);

The above code snippet has a delay loop of 100 microseconds, which is the maximum startup time for the Audio PLL module. The code has the PADEN bit set, which makes the AUDIOPINCLK signal available on the CLK_AUDIO pin.

To use AUDIOPLLCK as the clock source for an audio peripheral, it has to be enabled in the power manager. For example, the following line of code enables AUDIOPLLCK as the clock source for the PDMIC peripheral.

PMC->PMC_PCR = PMC_PCR_PID(ID_PDMIC) 
                | PMC_PCR_GCKCSS_AUDIO_CLK 
                | PMC_PCR_CMD 
                | PMC_PCR_EN 
                | PMC_PCR_GCKEN;