3 Pulse Density Modulation Interface Controller (PDMIC)

The PDMIC peripheral is a mono PDM decoder module that decodes an incoming PDM sample stream. The PDMIC module takes either the system clock (MCK) or the generic clock (e.g., Audio PLL PMC output) as its clock source. It then generates the PDM clock on the PDMIC_CLK pin to be fed to the connected PDM microphone and samples the data from the PDMIC_DAT pin. The PDM data is sampled on the rising edge of the PDMIC_CLK signal.

The module can output either a 16-bit or a 32-bit signed result to the result register (PDMIC_CDR – PDMIC Converted Data Register), which can be transferred to the main memory either by the CPU or by the DMA controller. It embeds a FIFO buffer to store up to four converted results.

The PDMIC module incorporates a DSP engine containing a decimation filter, a droop compensation filter, a sixth-order low-pass filter, a first-order high-pass filter and an offset and gain compensation stage, as shown in the block diagram below.

The overall decimation ratio of the DSP engine is either 64 or 128, which is configurable. This means, to sample an audio signal with a sample rate of 48 kHz, the clock frequency to be given to the microphone over the PDMIC_CLK pin should be (48000 * 128) = 6.144 MHz if an oversampling ratio of 128 is used, or should be (48000 * 64) = 3.072 MHz if an oversampling ratio of 64 is used.

For a more detailed description of the individual components of the DSP engine, refer to "Digital Signal Processing (Digital Filter)" in Section "Pulse Density Modulation Interface Controller (PDMIC)" of the SAMA5D2 device data sheet.

The digital output, after all the decimation and filter stages, is fed to an offset and gain compensation stage, which follows the equation below.

d_{o u t} = \frac{(d_{i n} + (o f f s e t * 2^{8})) * d g a i n}{2^{(s c a l e + s h i f t + 8)}}

Where:

d_in is the output from the filter stages (signed 24-bit) and input to the offset and gain compensation stage.
d_out is the final output which will be placed in the PDMIC_CDR register.
offset is a signed 16-bit integer which is multiplied by 2⁸ to have the same weight as d_in.
d_gain is an unsigned 15-bit integer which is set to 0 after reset. The user must configure this parameter to a non-zero value to get a valid result. The output after d_gain multiplication of d_in (with offset added) can be more than 32 bits in size. Only 32 MSB bits will be used for the next scaling and shifting stage.
scale and shift are unsigned 4-bit integers each. The multiplication result will be shifted right by (scale + shift + 8) bits.

When the 32-bit result mode is selected, the scaling and shifting stage division is not performed, and the 32-bit multiplication result (32-bit MSBs) is placed in the result register. When the 16-bit result mode is selected, the scaling and shifting stage division is performed. The result is then saturated to be within ±(2¹⁵ – 1), and the 16 LSBs of this saturation operation are placed in the result register.