2 Digital Audio Phase Locked Loop (Audio PLL)

The SAMA5D2 series includes a high-resolution fractional-N digital PLL designed for low-jitter operation. The PLL takes the reference clock signal from the main crystal oscillator and generates a high-frequency audio core clock output.

Figure 2-1. Audio PLL Block Diagram

The high-frequency audio core clock output is split internally into two signal paths, each having individual divider and clock gating networks. The output from one signal path is fed to the power manager (PMC), which is then used as the base clock (GCLK – Generic Clock) for audio peripherals like PDMIC, Class-D and I2SC. This output is the AUDIOPLLCK in the block diagram.

The output from the other signal path is fed to the audio clock output pin (CLK_AUDIO), which can be used as a master clock for external components like an external audio codec chip. This output is the AUDIOPINCLK in the block diagram.

The Audio PLL is designed to generate an internal audio core clock frequency in the range of 620 MHz (min) to 700 MHz (max). Refer to the Electrical Characteristics section in the SAMA5D2 Data Sheet. This frequency is controlled by the user-configurable parameters ND and FRACR, as shown in the equation below:

f a u d i o c o r e c l o c k = f r e f N D + 1 +   F R A C R 2 22

fref is the reference input clock frequency from the main crystal oscillator, which should be a minimum of 12 MHz and a maximum of 24 MHz. The fractional part in the above equation plays a key role in high-resolution frequency adjustment. The maximum frequency resolution achievable is 2.8610 Hz. This means that for each increment in the FRACR value, the audio core clock output, typically in the 620-700 MHz range, is incremented by 2.8610 Hz.

The AUDIOPLLCK path has a divider that is controlled by the user-configurable parameter QDPMC. The output frequency from the AUDIOPLLCK path is given by the equation below.

f a u d i o p l l c k = f a u d i o c o r e c l o c k ( Q D P M C + 1 )

The AUDIOPINCLK path has a divider which is controlled by the user-configurable parameters DIV and QDAUDIO. The output frequency is given by the equation below.

f a u d i o p i n c l k = f a u d i o c o r e c l o c k ( D I V * Q D A U D I O )

The DIV and QDAUDIO parameters should be configured in such a way that faudiopinclk is in the range of 8 MHz (min) to 48 MHz (max).

The Audio PLL output can be varied during runtime by adjusting the FRACR and ND values. The high FRACR resolution allows very fine and smooth frequency adjustments without audible artifacts. For example, in a network application, it is possible to adjust FRACR so that the local audio clock frequency tracks a distant master clock in the network. On the contrary, when making large changes to the output frequency (e.g., when changing ND), it is good practice to first mute the relevant audio signals of the system and then let the PLL settle to the new frequency to avoid any undesirable noise. In any case, the settling time of the PLL to reach a new frequency value is a maximum of 100 µs. Refer to the Electrical Characteristics section in the SAMA5D2 Data Sheet.