1.8.3 Clock Generator (CLOCK)

The Clock Generator is made up of:

  • Oscillators

    • A low-power 32.768 kHz oscillator supporting crystals, MEMs, resonators and Bypass mode

    • An embedded always-on, slow RC oscillator generating a typical 32 kHz clock

    • A 12 to 48 MHz oscillator supporting crystals, MEMs, resonators and Bypass mode

    • A Main RC oscillator generating a typical 12 MHz clock

  • Three fractional-N PLLs

It provides the following clocks:

  • MD SCLK - Monitoring Domain Slow clock, This clock sourced from the always-on Slow RC oscillator only, is the only permanent clock of the system and feeds safety-critical functions of the device.

  • TD SCLK - Timing Domain Slow clock. This clock, sourced from the 32. 768 kHz crystal oscillator or the always-on Slow RC oscillator, is routed to the RTC and RTT peripherals.

  • MAINCK - Output of the Main clock oscillator selection. This clock is either the Main crystal oscillator or Main RC oscillator.

  • PLL Clocks - Outputs of embedded PLLs

  • One SysTick external clock for each processor core

Using The Library

The Clock peripheral library initializes the clock system as configured by the user in the MCC easy view.

Library Interface

Clock Generator peripheral library provides the following interfaces:

Functions

Name Description
CLK_Initialize Initializes hardware of the System Clock and Peripheral Clock
CLK_TDSCLKSelectXTAL Selects 32KHz Crystal Oscillator as Slow Clock (SLCK) source
CLK_EnableMainRCOscillator Enables main RC oscillator
CLK_DisableMainRCOscillator Disables main RC oscillator
CLK_EnableMainXTALOscillator Enables main XTAL oscillator
CLK_DisableMainXTALOscillator Disables main XTAL oscillator
CLK_MainOscillatorSelectXTAL Selects XTAL as main oscillator source
CLK_MainOscillatorSelectRC Selects RC oscillator as main coscillator source
CLK_PLLEnable Enables PLL
CLK_PLLDisable Disbales PLL
CLK_PLLConfig Configures given PLL parameters
CLK_Core0ClkConfig Configures core 0 clock parameters
CLK_Core1BusMasterClkEnable Enables core 1 master clock
CLK_Core1BusMasterClkDisable Disables core 1 master clock
CLK_Core1ClkConfig Configures core 1 clock parameters
CLK_Core1ProcessorClkEnable Enables core 1 processor clock
CLK_Core1ProcessorClkDisable Disables core 1 processor clock
CLK_PCKConfig Configures programmable clock parameters
CLK_PCKOutputEnable Enables PCK output
CLK_PCKOutputDisable Disables PCK output
CLK_PeripheralClockConfigGet Reads peripheral clock parameters
CLK_PeripheralClockConfigSet Configures peripheral clock parameters