27.5.13 Slave Data
| Name: | SDATA |
| Offset: | 0x0D |
| Reset: | 0x00 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DATA[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 7:0 – DATA[7:0] Data
This bit field provides access to the slave data register.
Reading valid data or writing data to be transmitted can only be
successfully achieved when the SCL is held low by the slave (i.e., when the
slave CLKHOLD bit is set to ‘1’). It is not necessary to check
the Clock Hold (CLKHOLD) bit from the Slave Status (TWIn.SSTATUS) register in
software before accessing the SDATA register if the software keeps track of the
present protocol state by using interrupts or observing the interrupt flags.
If the Smart Mode Enable (SMEN) bit in the Slave Control A
(TWIn.SCTRLA) register is set to ‘1’, a read access to the
SDATA register, when the clock hold is active, auto-triggers bus operations and
will command the slave to perform an acknowledge action. This is dependent on
the setting of the Acknowledge Action (ACKACT) bit from the Slave Control B
(TWIn.SCTRLB) register.