27.5.6 Master Baud Rate

Name: MBAUD
Offset: 0x06
Reset: 0x00
Property: -

Bit 76543210 
 BAUD[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bits 7:0 – BAUD[7:0] Baud Rate

This bit field is used to derive the SCL high and low time. It must be written while the master is disabled. The master can be disabled by writing ‘0’ to the Enable TWI Master (ENABLE) bit from the Master Control A (TWIn.MCTRLA) register.

Refer to the 27.3.2.2.1 Clock Generation section for more information on how to calculate the frequency of the SCL.