27.5.9 Slave Control A
| Name: | SCTRLA |
| Offset: | 0x09 |
| Reset: | 0x00 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DIEN | APIEN | PIEN | PMEN | SMEN | ENABLE | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 7 – DIEN Data Interrupt Enable
Writing this bit to ‘1’ enables an interrupt on the
Data Interrupt Flag (DIF) from the Slave Status (TWIn.SSTATUS) register.
A TWI slave data interrupt will be generated only if this bit, the
DIF flag, and the Global Interrupt Enable (I) bit in Status (CPU.SREG) register
are all ‘1’.
Bit 6 – APIEN Address or Stop Interrupt Enable
Writing this bit to ‘1’ enables an interrupt on the
Address or Stop Interrupt Flag (APIF) from the Slave Status (TWIn.SSTATUS)
register.
A TWI slave address or stop interrupt will be generated only if this
bit, the APIF flag, and the Global Interrupt Enable (I) bit in the Status
(CPU.SREG) register are all ‘1’.
- The slave stop interrupt shares the interrupt flag and vector with the slave address interrupt.
- The Stop Interrupt Enable
(PIEN) bit in the Slave Control A (TWIn.SCTRLA) register must be written
to ‘
1’ for the APIF to be set on a Stop condition. - When the interrupt occurs, the Address or Stop (AP) bit in the Slave Status (TWIn.SSTATUS) register will determine whether an address match or a Stop condition caused the interrupt.
Bit 5 – PIEN Stop Interrupt Enable
Writing this bit to ‘1’ allows the Address or Stop
Interrupt Flag (APIF) in the Slave Status (TWIn.SSTATUS) register to be set when
a Stop condition occurs. To use this feature, the main clock frequency must be
at least four times the SCL frequency.
Bit 2 – PMEN Address Recognition Mode
If this bit is written to ‘1’, the slave address
match logic responds to all received addresses.
If this bit is written to ‘0’, the address match
logic uses the Slave Address (TWIn.SADDR) register to determine which address to
recognize as the slave’s address.
Bit 1 – SMEN Smart Mode Enable
Writing this bit to ‘1’ enables the slave Smart
mode. When the Smart mode is enabled, issuing a command by writing to the
Command (SCMD) bit field in the Slave Control B (TWIn.SCTRLB) register or
accessing the Slave Data (TWIn.SDATA) register resets the interrupt, and the
operation continues. If the Smart mode is disabled, the slave always waits for a
new slave command before continuing.
Bit 0 – ENABLE Enable TWI Slave
Writing this bit to ‘1’ enables the TWI slave.