7.2 Internal Multiplexed Signals

PA20, PB00, PB15, PB30, PB31, PC16, PC18 and PC19 are controlled by the PORT as general purpose I/O by default and, alternatively, may be assigned to one of the peripheral functions A, B, C, D, E, F, G or H. To enable a peripheral function on a pin, the Peripheral Multiplexer Enable bit in the Pin Configuration register corresponding to that pin (PINCFGn.PMUXEN, n = 0-31) in the PORT must be written to one. The selection of peripheral functions A to H is done by writing to the Peripheral Multiplexing Odd and Even bits in the Peripheral Multiplexing register (PMUXn.PMUXE/O) in the PORT.

PA10, PA11, PB16 and PB17 cannot be configured as output ports. These ports are always connected to the RFCTRL inputs.

Table 7-2. Internal Multiplexed Signals
A A B B B B B C D E F G H I

Internal

Signal

IO Pin Supply Type EIC RSTC REF ADC AC

PTC

X-lines

PTC

Y-lines

SERCOM SERCOM-ALT

TC/

TCC

FECTRL/

TCC/

SERCOM

COM

AC/

GCLK

CCL
DIG3 PA10 VDDIO Input EXTINT[10] AIN[18] X[2] Y[8] SERCOM0/PAD[2] SERCOM2/PAD[2] TCC1/WO[0] TCC0/WO[2] GCLK_IO[4] CCL1/IN[5]
DIG4 PA11 VDDIO Input EXTINT[11] AIN[19] X[3] Y[9] SERCOM0/PAD[3] SERCOM2/PAD[3] TCC1/WO[1] TCC0/WO[3] GCLK_IO[5] CCL1/OUT[1]
SLP_TR PA20 VDDIO I/O EXTINT[4] X[8] SERCOM5/PAD[2] SERCOM3/PAD[2] TC3/WO[0] TCC0/WO[6] GCLK_IO[4]
IRQ PB00 VDDANA I/O EXTINT[0] AIN[8] SERCOM5/PAD[2] TC3/WO[0] SUPC/PSOK CCL0/IN[1]
RSTN PB15 VDDIO I/O EXTINT[15] X[15] SERCOM4/PAD[3] TC1/WO[1] GCLK_IO[1] CCL3/IN[10]
DIG1 PB16 VDDIO Input EXTINT[0] SERCOM5/PAD[0] TC2/WO[0] TCC0/WO[4] GCLK_IO[2] CCL3/IN[11]
DIG2 PB17 VDDIO Input EXTINT[1] SERCOM5/PAD[1] TC2/WO[1] TCC0/WO[5] GCLK_IO[3] CCL3/OUT[3]
MOSI PB30 VDDIO I/O EXTINT[14] SERCOM5/PAD[0] TCC0/WO[0] SERCOM4/PAD[2]
SEL PB31 VDDIO I/O EXTINT[15] SERCOM5/PAD[1] TCC0/WO[1] SERCOM4/PAD[1]
CLKM PC16 VDDIO I/O GCLK_IO[1]
SCLK PC18 VDDIO I/O SERCOM4/PAD[3]
MISO PC19 VDDIO I/O SERCOM4/PAD[0]