13.15.6.3 External Pin Processing

Each external pin can be configured to generate an interrupt/event on edge detection (rising, falling or both edges) or level detection (high or low). The sense of external interrupt pins is configured by writing the Input Sense x bits in the Config n register (CONFIGn.SENSEx) (CONFIGn). The corresponding interrupt flag (INTFLAG.EXTINT[x]) in the Interrupt Flag Status and Clear register (INTFLAG) is set when the interrupt condition is met.

When the interrupt flag is cleared in edge-sensitive mode, INTFLAG.EXTINT[x] will only be set if a new interrupt condition is met. In level-sensitive mode, when the interrupt is cleared, INTFLAG.EXTINT[x] will be set immediately if the EXTINTx pin still matches the interrupt condition.

Each external pin can be filtered by a majority vote filtering, clocked by GCLK_EIC or CLK_ULP32K. Filtering is enabled if bit Filter Enable x in the Configuration n register (CONFIGn.FILTENx) (CONFIGn) is written to '1'. The majority vote filter samples the external pin three times with GCLK_EIC or CLK_ULP32K and outputs the value when two or more samples are equal.

Table 13-41. Majority Vote Filter
Samples [0, 1, 2] Filter Output
[0,0,0] 0
[0,0,1] 0
[0,1,0] 0
[0,1,1] 1
[1,0,0] 0
[1,0,1] 1
[1,1,0] 1
[1,1,1] 1

When an external interrupt is configured for level detection and when filtering is disabled, detection is done asynchronously. Asynchronous detection does not require GCLK_EIC or CLK_ULP32K, but interrupt and events can still be generated.

If filtering or edge detection is enabled, the EIC automatically requests GCLK_EIC or CLK_ULP32K to operate. The selection between these two clocks is done by writing the Clock Selection bits in the Control A register (CTRLA.CKSEL). GCLK_EIC must be enabled in the GCLK module.

Figure 13-64. Interrupt Detections

The detection delay depends on the detection mode.

Table 13-42. Interrupt Latency
Detection mode Latency (worst case)
Level without filter Five CLK_EIC_APB periods
Level with filter Four GCLK_EIC/CLK_ULP32K periods + five CLK_EIC_APB periods
Edge without filter Four GCLK_EIC/CLK_ULP32K periods + five CLK_EIC_APB periods
Edge with filter Six GCLK_EIC/CLK_ULP32K periods + five CLK_EIC_APB periods