13.25.8.7.5 Host Status Bank
Original offset 0x0A & 0x1A
Name: | STATUS_BK |
Offset: | 0x0A |
Reset: | 0xXXXXXXX |
Property: | NA |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
ERRORFLOW | CRCERR | ||||||||
Access | R/W | R/W | |||||||
Reset | x | x |
Bit 1 – ERRORFLOW Error Flow Status
This bit defines the Error Flow Status.
This bit is set when a Error Flow has been detected during transfer from/towards this bank.
For IN transfer, a NAK handshake has been received. For OUT transfer, a NAK handshake has been received. For Isochronous IN transfer, an overrun condition has occurred. For Isochronous OUT transfer, an underflow condition has occurred.
Value | Description |
---|---|
0 | No Error Flow detected. |
1 | A Error Flow has been detected. |
Bit 0 – CRCERR CRC Error
This bit defines the CRC Error Status.
This bit is set when a CRC error has been detected in an isochronous IN endpoint bank.
Value | Description |
---|---|
0 | No CRC Error. |
1 | CRC Error detected. |