13.6.6.2.4 Selecting the Synchronous Clock Division Ratio

The main clock, CLK_MAIN, feeds an 8-bit prescaler that can be used to generate the synchronous clocks. By default, the synchronous clocks run on the undivided main clock. The user can select a prescaler division for the CPU clock domain by writing the Division (DIV) bits in the CPU Clock Division register CPUDIV, resulting in a CPU clock domain frequency determined by this equation:

f C P U = f m a i n C P U D I V

If the application attempts to write forbidden values in the CPUDIV and LPDIV registers, the registers are written but these bad values are not used, and a violation is reported to the PAC module.

Division bits (DIV) can be written without halting or disabling peripheral modules. Writing DIV bits allows a new clock setting to be written to all synchronous clocks belonging to the corresponding clock domain at the same time.

Figure 13-17. Synchronous Clock Selection and Prescaler

References:

15 Electrical Characteristics

13.1 PAC - Peripheral Access Controller