13.12.8.8 Clear

Name: CLEAR
Offset: 0x0C
Reset: 0x00
Property: Write-Synchronized

Bit 76543210 
 CLEAR[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bits 7:0 – CLEAR[7:0] Watchdog Clear

In Normal mode, writing 0xA5 to this register during the watchdog time-out period will clear the Watchdog Timer and the watchdog time-out period is restarted.

In Window mode, any writing attempt to this register before the time-out period started (i.e., during TOWDTW) will issue an immediate system Reset. Writing 0xA5 during the time-out period TOWDT will clear the Watchdog Timer and the complete time-out sequence (first TOWDTW then TOWDT) is restarted.

In both modes, writing any other value than 0xA5 will issue an immediate system Reset.