2.5 On-Chip ROM Code Boot Process

When the chip is powered on, the processor clock (CPU_CLK) and main system bus clock (MCK) source is the main clock (MAINCK).

The ROM code performs a low-level initialization as follows:

  1. The PLLA is initialized at a frequency of 1200 MHz.
  2. The main system bus clock is selected: when the PLLA is stabilized, the main system bus clock source switches from the internal RC 12 MHz main clock to the PLLA clock divided by two. The CPU_CLK frequency is then half of the PLLA clock, whereas the MCK frequency is 200 MHz.
Note: No external crystal or clock is needed during the external boot memory sequence. An external clock source is checked before the launch of the SAM-BA® Monitor to obtain a more accurate clock for USB.
Table 2-1. ROM Code Clock Scheme
ClockFrequency (MHz)
PLLA1200
CPU_CLK600
MCK200
Figure 2-1. ROM Code Boot Flow

After the chip initialization, the ROM code evaluates the Boot Configuration Packet and Secure Boot Configuration Packet, if provisioned, to select the boot flow as shown in the figure above.