47.7.7 QSPI Interrupt Disable Register
This register can only be
written if the WPITEN bit is cleared in the QSPI Write Protection Mode Register.
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Disables the corresponding interrupt.
| Name: | QSPI_IDR |
| Offset: | 0x18 |
| Reset: | – |
| Property: | Write-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| | | | | | | | | | |
| Access | | | | | | | | | |
| Reset | | | | | | | | | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| | | | | | | | | | |
| Access | | | | | | | | | |
| Reset | | | | | | | | | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| | | | | | | INSTRE | CSS | CSR | |
| Access | | | | | | W | W | W | |
| Reset | | | | | | – | – | – | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | | | | | OVRES | TXEMPTY | TDRE | RDRF | |
| Access | | | | | W | W | W | W | |
| Reset | | | | | – | – | – | – | |
Bit 10 – INSTRE Instruction End Interrupt Disable
Bit 9 – CSS Chip Select Status Interrupt Disable
Bit 8 – CSR Chip Select Rise Interrupt Disable
Bit 3 – OVRES Overrun Error Interrupt Disable
Bit 2 – TXEMPTY Transmission Registers Empty Disable
Bit 1 – TDRE Transmit Data Register Empty Interrupt Disable
Bit 0 – RDRF Receive Data Register Full Interrupt Disable
