43.7.2 CLASSD Mode Register
This register can only be written if the WPEN bit is cleared in the CLASSD Write Protection Mode Register.
| Name: | CLASSD_MR |
| Offset: | 0x04 |
| Reset: | 0x00010022 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| NOVRVAL[1:0] | NON_OVERLAP | ||||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 1 | ||||||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| PWMTYP | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RMUTE | REN | LMUTE | LEN | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 1 | 0 | 1 | 0 |
Bits 21:20 – NOVRVAL[1:0] Non-Overlapping Value
| Value | Name | Description |
|---|---|---|
| 0 | 5NS | Non-overlapping time is 5 ns |
| 1 | 10NS | Non-overlapping time is 10 ns |
| 2 | 15NS | Non-overlapping time is 15 ns |
| 3 | 20NS | Non-overlapping time is 20 ns |
Bit 16 – NON_OVERLAP Non-Overlapping Enable
| Value | Description |
|---|---|
| 0 | Non-overlapping circuit is disabled. |
| 1 | Non-overlapping circuit is enabled. |
Bit 8 – PWMTYP PWM Modulation Type
0 (TRAILING_EDGE): The signal is single-ended.
If NON_OVERLAP is cleared, the signal is sent to CLASSD_L0 and CLASSD_R0 (see figure Use Case 4A or figure Use Case 4B).
If NON_OVERLAP is set, the signal is sent to CLASSD_L0/L1 and CLASSD_R0/R1 (see figure Use Case 2).
1 (UNIFORM): The signal is differential.
If NON_OVERLAP is cleared, the signal is sent to CLASSD_L0/L2 and CLASSD_R0/R2 (see figure Use Case 3A or figure Use Case 3B).
If NON_OVERLAP is set, the signal is sent to CLASSD_L0/L1/L2/L3 and CLASSD_R0/R1/R2/R3 (see figure Use Case 1).
Bit 5 – RMUTE Right Channel Mute
| Value | Description |
|---|---|
| 0 | Right channel is unmuted. |
| 1 | Right channel is muted. |
Bit 4 – REN Right Channel Enable
| Value | Description |
|---|---|
| 0 | Right channel is disabled. |
| 1 | Right channel is enabled. |
Bit 1 – LMUTE Left Channel Mute
| Value | Description |
|---|---|
| 0 | Left channel is unmuted. |
| 1 | Left channel is muted. |
Bit 0 – LEN Left Channel Enable
| Value | Description |
|---|---|
| 0 | Left channel is disabled. |
| 1 | Left channel is enabled. |