43.7.3 CLASSD Interpolator Mode Register
This register can only be written if the WPEN bit is cleared in the CLASSD Write Protection Mode Register.
| Name: | CLASSD_INTPMR |
| Offset: | 0x08 |
| Reset: | 0x00304E4E |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| MONOMODE[1:0] | MONO | EQCFG[3:0] | |||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| FRAME[2:0] | SWAP | DEEMP | DSPCLKFREQ | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 1 | 1 | 0 | 0 | 0 | |||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| ATTR[6:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 1 | 0 | 0 | 1 | 1 | 1 | 0 | ||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ATTL[6:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 1 | 0 | 0 | 1 | 1 | 1 | 0 | ||
Bits 30:29 – MONOMODE[1:0] Mono Mode Selection
Defines which signal is sent to both channels when the MONO bit is set.
| Value | Name | Description |
|---|---|---|
| 0 | MONOMIX | (left + right) / 2 is sent to both channels |
| 1 | MONOSAT | (left + right) is sent to both channels. If the sum is too high, the result is saturated. |
| 2 | MONOLEFT | THR[15:0] is sent to both the left and the right channels |
| 3 | MONORIGHT | THR[31:16] is sent to both the left and the right channels |
Bit 28 – MONO Mono Signal
0 (DISABLED): The signal is sent stereo to the left and right channels.
1 (ENABLED): The same signal is sent to both the left and the right channels. The sent signal is defined by the MONOMODE field value.
Bits 27:24 – EQCFG[3:0] Equalization Selection
| Value | Name | Description |
|---|---|---|
| 0 | FLAT | Flat response |
| 1 | BBOOST12 | Bass boost +12 dB |
| 2 | BBOOST6 | Bass boost +6 dB |
| 3 | BCUT12 | Bass cut -12 dB |
| 4 | BCUT6 | Bass cut -6 dB |
| 5 | MBOOST3 | Medium boost +3 dB |
| 6 | MBOOST8 | Medium boost +8 dB |
| 7 | MCUT3 | Medium cut -3 dB |
| 8 | MCUT8 | Medium cut -8 dB |
| 9 | TBOOST12 | Treble boost +12 dB |
| 10 | TBOOST6 | Treble boost +6 dB |
| 11 | TCUT12 | Treble cut -12 dB |
| 12 | TCUT6 | Treble cut -6 dB |
Bits 22:20 – FRAME[2:0] CLASSD Incoming Data Sampling Frequency
| Value | Name | Description |
|---|---|---|
| 0 | FRAME_8K | 8 kHz |
| 1 | FRAME_16K | 16 kHz |
| 2 | FRAME_32K | 32 kHz |
| 3 | FRAME_48K | 48 kHz |
| 4 | FRAME_96K | 96 kHz |
| 5 | FRAME_22K | 22.05 kHz |
| 6 | FRAME_44K | 44.1 kHz |
| 7 | FRAME_88K | 88.2 kHz |
Bit 19 – SWAP Swap Left and Right Channels
0 (LEFT_ON_LSB): Left channel is on CLASSD_THR[15:0], right channel is on CLASSD_THR[31:16].
1 (RIGHT_ON_LSB): Right channel is on CLASSD_THR[15:0], left channel is on CLASSD_THR[31:16].
Bit 18 – DEEMP Enable De-emphasis Filter
0 (DISABLED): De-emphasis filter is disabled.
1 (ENABLED): De-emphasis filter is enabled.
Bit 16 – DSPCLKFREQ DSP Clock Frequency
0 (12M288): DSP Clock (DSPCLK) is 12.288 MHz.
1 (11M2896): DSP Clock (DSPCLK) is 11.2896 MHz.
Bits 14:8 – ATTR[6:0] Right Channel Attenuation
Right channel attenuation is defined as follows:
– if ATTR ≤ 77 the attenuation is -ATTR dB
– else the right signal is muted
Bits 6:0 – ATTL[6:0] Left Channel Attenuation
Left channel attenuation is defined as follows:
– if ATTL ≤ 77 the attenuation is -ATTL dB
– else the left signal is muted