53.5.1 AES Control Register
This register can only be written if the WPCREN bit is cleared in the AES Write Protection Mode Register.
| Name: | AES_CR |
| Offset: | 0x00 |
| Reset: | – |
| Property: | Write-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| UNLOCK | |||||||||
| Access | W | ||||||||
| Reset | – |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| SWRST | |||||||||
| Access | W | ||||||||
| Reset | – |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| START | |||||||||
| Access | W | ||||||||
| Reset | – |
Bit 24 – UNLOCK Unlock Processing
AES_WPSR must be cleared before performing the unlock command.
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Unlocks the processing in case of abnormal event detection if AES_WPMR.ACTION > 0. |
Bit 8 – SWRST Software Reset
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Resets the AES. A software-triggered reset of the AES interface is performed. |
Bit 0 – START Start Processing
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Starts manual encryption/decryption process. |