53.5.17 AES Extended Mode Register
This register can only be written if the WPEN bit is cleared in the AES Write Protection Mode Register.
| Name: | AES_EMR |
| Offset: | 0xB0 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| BPE | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| NHEAD[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| PADLEN[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PKRS | PLIPD | PLIPEN | APM | APEN | |||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 |
Bit 31 – BPE Block Processing End
| Value | Description |
|---|---|
| 0 | AES_ISR.DATRDY flag reports only the end message encryption processing. No intermediate block processing is reported when SMOD=2. When a DMA is used to transfer data, BPE must be cleared. |
| 1 | AES_ISR.DATRDY flag reports each end of block processing when SMOD=2. When AES_IDATARx are not loaded by a DMA and SMOD=2, this bit can be written to 1 to rise the AES_ISR.DATRDY flag when a new data block can be written. |
Bits 23:16 – NHEAD[7:0] IPSec Next Header
| Value | Description |
|---|---|
| 0–255 | IPSec Next Header field |
Bits 15:8 – PADLEN[7:0] Auto Padding Length
| Value | Description |
|---|---|
| 0–255 | Padding length in bytes |
Bit 7 – PKRS Private Key Internal Register Select
| Value | Description |
|---|---|
| 0 |
The key used by the AES is in the AES_KEYWRx registers. |
| 1 |
The key used by the AES is in the Private Key internal registers written through the Private Key bus. |
Bit 5 – PLIPD Protocol Layer Improved Performance Decipher
| Value | Description |
|---|---|
| 0 | Protocol layer improved performance is in ciphering mode. |
| 1 | Protocol layer improved performance is in deciphering mode. |
Bit 4 – PLIPEN Protocol Layer Improved Performance Enable
| Value | Description |
|---|---|
| 0 | Protocol layer improved performance is disabled. |
| 1 | Protocol layer improved performance is enabled. |
Bit 1 – APM Auto Padding Mode
| Value | Description |
|---|---|
| 0 | Auto Padding performed according to IPSec standard. |
| 1 | Auto Padding performed according to SSL standard. |
Bit 0 – APEN Auto Padding Enable
| Value | Description |
|---|---|
| 0 | Auto Padding feature is disabled. |
| 1 | Auto Padding feature is enabled. |