25.10.3 MATRIX Priority Register A For Clients x
This register can only be written if the WPEN bit is cleared in the Write Protection Mode Register.
| Registers | Reset Values |
|---|---|
| PRAS0, PRAS3, PRAS7, PRAS8, PRAS9 | 0x00007722 |
| PRAS1, PRAS2, PRAS10, PRAS11, PRAS12 | 0x00000022 |
| PRAS4 | 0x00000702 |
| PRAS5 | 0x00007020 |
| PRAS6 | 0x00000000 |
| Name: | MATRIX_PRASx |
| Offset: | 0x80 + x*0x08 [x=0..12] |
| Reset: | – |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| LQOSEN7 | M7PR[1:0] | LQOSEN6 | M6PR[1:0] | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | – | – | – | – | – | – | |||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| LQOSEN5 | M5PR[1:0] | LQOSEN4 | M4PR[1:0] | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | – | – | – | – | – | – | |||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| LQOSEN3 | M3PR[1:0] | LQOSEN2 | M2PR[1:0] | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | – | – | – | – | – | – | |||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| LQOSEN1 | M1PR[1:0] | LQOSEN0 | M0PR[1:0] | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | – | – | – | – | – | – | |||
Bits 2, 6, 10, 14, 18, 22, 26, 30 – LQOSENx Latency Quality of Service Enable for Host x
| Value | Description |
|---|---|
| 0 | Disables propagation of Latency Quality of Service from the Host x to the Client and apply MxPR priority for all access from Host x to the Client. |
| 1 | Enables the propagation of Latency Quality of Service from the Host x to the Client if supported by the Host x. |
Bits 0:1, 4:5, 8:9, 12:13, 16:17, 20:21, 24:25, 28:29 – MxPR Host x Priority
Fixed priority of Host x for accessing the selected client. The higher the number, the higher the priority.
All the hosts programmed with the same MxPR value for the client make up a priority pool.
Round-robin arbitration is used in the lowest (MxPR = 0) and highest (MxPR = 3) priority pools.
Fixed priority is used in intermediate priority pools (MxPR = 1) and (MxPR = 2).
See Arbitration Priority Scheme for details.
If LQOSENx bit is cleared, then this priority value is used as it for arbitration and downward propagation to the client. If LQOSENx bit is set, then this priority acts as the upper limit for the Latency Quality of Service from Host x.
For hosts other than the CPU, the usual value of this field should be 0x0 if LQOSENx bit is cleared, and 0x1 if LQOSENx bit is set. For the CPU host, the usual value of this field should be 0x2.