7.2.4.1 DDR/SDR I/O Calibration

The DDR/SDR I/Os embed an automatic impedance matching control to avoid overshoots and reach the best performance levels depending on the bus load and external memories. A serial termination connection scheme, where the driver has an output impedance matched to the characteristic impedance of the line, is used to improve signal quality and reduce EMI.

One specific analog input, DDR_CAL, is used to calibrate all DDR/SDR I/Os.

The MPDDRC and SDRAMC support the ZQ calibration procedure used to calibrate the SAM9X60 DDR/SDR I/O drive strength and the commands to set up the external memory device drive strength (refer to DDR-SDRAM Controller (MPDDRC)). The calibration cell supports all the supported memory types. Calibration is performed in the initialization phase only.

Figure 7-2. DDR Calibration Cell

The calibration cell provides an input pin, DDR_CAL, loaded with one of the following resistor RZQ values:

20 KΩ for LPDDR
20 KΩ for DDR2
16.9 KΩ for SDR
20 KΩ for LPSDR

The typical value for CZQ is 22 pF.