21.6.2 PIT64B Mode Register

This register can only be written if the WPEN bit is cleared in the PIT64B Write Protection Mode Register.

When the timer is running, writing a value to this register has no effect. The value written is this register is loaded anytime before a START command is issued.

Name: PIT64B_MR
Offset: 0x04
Reset: 0x00000000
Property: Read/Write

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
     PRESCALER[3:0] 
Access R/WR/WR/WR/W 
Reset 0000 
Bit 76543210 
    SMODSGCLK  CONT 
Access R/WR/WR/W 
Reset 000 

Bits 11:8 – PRESCALER[3:0] Prescaler Period

ValueDescription
0

A prescaler divider of 1 is used.
1-15

The 64-bit timer is incremented at each (PRESCALER+1)x selected period (see SGCLK).

Bit 4 – SMOD Start Mode

ValueDescription
0

Writing PIT64B_LSBPR does not start the timer period.
1

Writing PIT64B_LSBPR starts the timer period.

Bit 3 – SGCLK Generic Clock Selection Enable

If GCLK is asynchronous to the peripheral clock, a jitter of 1 peripheral clock period is created on the periodic interval event when Continuous mode is selected.
ValueDescription
0

The prescaler is triggered at each rising edge of “Peripheral clock” and the timer is triggered.
1

GCLK clock is selected as clock source of the 8-bit prescaler.

Bit 0 – CONT Continuous Mode

ValueDescription
0

A single period interrupt is generated from a START command.
1

Continuous periodic interrupts are generated after a single START command.