46.7.1.3 Baud Rate in Synchronous Mode

If the USART is programmed to operate in Synchronous mode, the selected clock is simply divided by the CD field in FLEX_US_BRGR:

In Synchronous mode, if the external clock is selected (USCLKS = 3) and CLKO = 0 (Client mode), the clock is provided directly by the signal on the USART SCK pin. No division is active. The value written in FLEX_US_BRGR has no effect. When operating in asynchronous modes and the SCK pin is selected for baud rate generation, the external clock frequency must be at least three times lower than the system clock.

In Half-duplex Synchronous Host mode (SYNC=1, USCLKS = 3, CLKO=1), the transmit path (TXD) can be operated at f_{peripheral clock}/3.

In Full-duplex Synchronous Host mode (SYNC=1, USCLKS = 3, CLKO=1) or in Synchronous Client mode (SYNC=1, USCLKS = 3, CLKO=0), SCK must be lower than f_{peripheral clock}/6.

When either the external clock SCK or the internal clock divided (peripheral clock/DIV or GCLK) is selected and if the user has to ensure a 50:50 mark/space ratio on the SCK pin, the value programmed in CD must be even. If the peripheral clock is selected and if the value programmed in CD is odd, the baud rate generator ensures a 50:50 duty cycle on the SCK pin.