20.5.1 Periodic Interval Timer Mode Register
This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode Register (SYSC_WPMR).
| Name: | PIT_MR |
| Offset: | 0x00 |
| Reset: | 0x000FFFFF |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| PITIEN | PITEN | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| PIV[19:16] | |||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 1 | 1 | 1 | 1 | |||||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| PIV[15:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PIV[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |
Bit 25 – PITIEN Period Interval Timer Interrupt Enable
| Value | Description |
|---|---|
| 0 |
The bit PITS in PIT_SR has no effect on the interrupt. |
| 1 |
The bit PITS in PIT_SR asserts an interrupt. |
Bit 24 – PITEN Period Interval Timer Enabled
| Value | Description |
|---|---|
| 0 |
The Periodic Interval Timer is disabled when the PIV value is reached. |
| 1 |
The Periodic Interval Timer is enabled. |