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Ultra-Low Power Arm® ARM926EJ-S™ Processor-Based MPU, 600 MHz, Camera, LCD, 2D Graphics, Dual 10/100 Ethernet, CAN, USB, QSPI, FLEXCOMs, AES, SHA
Ultra-Low Power Arm® ARM926EJ-S™ Processor-Based MPU, 600 MHz, Camera, LCD, 2D Graphics, Dual 10/100 Ethernet, CAN, USB, QSPI, FLEXCOMs, AES, SHA
Product Pages
SAM9X60
  1. Home
  2. 46 Flexible Serial Communication Controller (FLEXCOM)
  3. 46.9 TWI Functional Description
  4. 46.9.6 TWI FIFOs
  5. 46.9.6.4 Sending/Receiving with FIFO Enabled in Client Mode

  • Introduction
  • Features
  • Reference Document
  • 1 Configuration Summary
  • 2 Block Diagram
  • 3 Signal Description
  • 4 Microchip Recommended Power Management Solutions
  • 5 Safety and Security Features
  • 6 Package and Pinout
  • 7 Memories
  • 8 System Controller
  • 9 Peripherals
  • 10 ARM926EJ-S Processor
  • 11 Debug and Test
  • 12 Boot Strategies
  • 13 System Controller Write Protection (SYSCWP)
  • 14 General Purpose Backup Registers (GPBR)
  • 15 Watchdog Timer (WDT)
  • 16 Reset Controller (RSTC)
  • 17 Real-Time Timer (RTT)
  • 18 Real-Time Clock (RTC)
  • 19 Shutdown Controller (SHDWC)
  • 20 Periodic Interval Timer (PIT)
  • 21 64-bit Periodic Interval Timer (PIT64B)
  • 22 Debug Unit (DBGU)
  • 23 OTP Memory Controller (OTPC)
  • 24 Special Function Registers (SFR)
  • 25 Bus Matrix (MATRIX)
  • 26 Advanced Interrupt Controller (AIC)
  • 27 Slow Clock Controller (SCKC)
  • 28 Clock Generator
  • 29 Power Management Controller (PMC)
  • 30 Parallel Input/Output Controller (PIO)
  • 31 External Bus Interface (EBI)
  • 32 DDR-SDRAM Controller (MPDDRC)
  • 33 SDRAM Controller (SDRAMC)
  • 34 Static Memory Controller (SMC)
  • 35 Programmable Multibit Error Correction Code Controller (PMECC)
  • 36 Programmable Multibit ECC Error Location Controller (PMERRLOC)
  • 37 DMA Controller (XDMAC)
  • 38 LCD Controller (LCDC)
  • 39 2D Graphics Engine (GFX2D)
  • 40 Ethernet MAC 10/100 (EMAC)
  • 41 USB Device High Speed Port (UDPHS)
  • 42 USB Host High Speed Port (UHPHS)
  • 43 Audio Class D Amplifier (CLASSD)
  • 44 Inter-IC Sound Multi-Channel Controller (I2SMCC)
  • 45 Synchronous Serial Controller (SSC)
  • 46 Flexible Serial Communication Controller (FLEXCOM)
    • 46.1 Description
    • 46.2 Embedded Characteristics
    • 46.3 Block Diagram
    • 46.4 I/O Lines Description
    • 46.5 Product Dependencies
    • 46.6 Register Accesses
    • 46.7 USART Functional Description
    • 46.8 SPI Functional Description
    • 46.9 TWI Functional Description
      • 46.9.1 Transfer Format
      • 46.9.2 Modes of Operation
      • 46.9.3 Host Mode
      • 46.9.4 Multi-Host Mode
      • 46.9.5 Client Mode
      • 46.9.6 TWI FIFOs
        • 46.9.6.1 Overview
        • 46.9.6.2 Sending Data with FIFO Enabled
        • 46.9.6.3 Receiving Data with FIFO Enabled
        • 46.9.6.4 Sending/Receiving with FIFO Enabled in Client Mode
        • 46.9.6.5 Clearing/Flushing FIFOs
        • 46.9.6.6 TXRDY and RXRDY Behavior
        • 46.9.6.7 TWI Single Data Access
        • 46.9.6.8 TWI Multiple Data Access
        • 46.9.6.9 Transmit FIFO Lock
        • 46.9.6.10 FIFO Pointer Error
        • 46.9.6.11 FIFO Thresholds
        • 46.9.6.12 FIFO Flags
      • 46.9.7 TWI Comparison Function on Received Character
      • 46.9.8 Sniffer Mode
      • 46.9.9 TWI Register Write Protection
    • 46.10 Register Summary
  • 47 Quad Serial Peripheral Interface (QSPI)
  • 48 Secure Digital MultiMedia Card Controller (SDMMC)
  • 49 Image Sensor Interface (ISI)
  • 50 Controller Area Network (CAN)
  • 51 Timer Counter (TC)
  • 52 Pulse Width Modulation Controller (PWM)
  • 53 Advanced Encryption Standard (AES)
  • 54 Secure Hash Algorithm (SHA)
  • 55 Triple Data Encryption Standard (TDES)
  • 56 Random Number Generator (TRNG)
  • 57 Analog-to-Digital Controller (ADC)
  • 58 Electrical Characteristics
  • 59 Mechanical Characteristics
  • 60 Marking
  • 61 Ordering Information
  • 62 Revision History
  • Microchip Information

46.9.6.4 Sending/Receiving with FIFO Enabled in Client Mode

See Sending Data with FIFO Enabled and Receiving Data with FIFO Enabled for details.

Figure 46-136. Sending/Receiving Data with FIFO Enabled in Client Mode

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