23.6.5 OTPC Interrupt Enable Register

This register can only be written if the WPITEN bit is cleared in the OTPC Write Protection Mode Register.

The following configuration values are valid for all listed bit names of this register:

0: No effect.

1: Enables the corresponding interrupt.

Name: OTPC_IER
Offset: 0x10
Reset: –
Property: Write-only

Bit 3130292827262524 
    SECE     
Access W 
Reset – 
Bit 2322212019181716 
        KBERR 
Access W 
Reset – 
Bit 15141312111098 
  HDERRCOERRCKERREORFEOHEOFEOR 
Access WWWWWWW 
Reset ––––––– 
Bit 76543210 
 WERRIVERRLKERRPGERREOKTEOIEOLEOP 
Access WWWWWWWW 
Reset –––––––– 

Bit 28 – SECE Security and/or Safety Event Interrupt Enable

Bit 16 – KBERR Key Bus Error Interrupt Enable

Bit 14 – HDERR Hide Error Interrupt Enable

Bit 13 – COERR Corruption Error Interrupt Enable

Bit 12 – CKERR Checksum Check Error Interrupt Enable

Bit 11 – EORF End Of Refresh Interrupt Enable

Bit 10 – EOH End Of Hide Interrupt Enable

Bit 9 – EOF End Of Flush Interrupt Enable

Bit 8 – EOR End Of Read Interrupt Enable

Bit 7 – WERR Write Error Interrupt Enable

Bit 6 – IVERR Invalidation Error Interrupt Enable

Bit 5 – LKERR Locking Error Interrupt Enable

Bit 4 – PGERR Programming Error Interrupt Enable

Bit 3 – EOKT End Of Key Transfer Interrupt Enable

Bit 2 – EOI End Of Invalidation Interrupt Enable

Bit 1 – EOL End Of Locking Interrupt Enable

Bit 0 – EOP End Of Programming Interrupt Enable