23.6.6 OTPC Interrupt Disable Register

This register can only be written if the WPITEN bit is cleared in the OTPC Write Protection Mode Register.

The following configuration values are valid for all listed bit names of this register:

0: No effect.

1: Disables the corresponding interrupt.

Name: OTPC_IDR
Offset: 0x14
Reset: –
Property: Write-only

Bit 3130292827262524 
    SECE     
Access W 
Reset – 
Bit 2322212019181716 
        KBERR 
Access W 
Reset – 
Bit 15141312111098 
  HDERRCOERRCKERREORFEOHEOFEOR 
Access WWWWWWW 
Reset ––––––– 
Bit 76543210 
 WERRIVERRLKERRPGERREOKTEOIEOLEOP 
Access WWWWWWWW 
Reset –––––––– 

Bit 28 – SECE Security and/or Safety Event Interrupt Disable

Bit 16 – KBERR Key Bus Error Interrupt Disable

Bit 14 – HDERR Hide Error Interrupt Disable

Bit 13 – COERR Corruption Error Interrupt Disable

Bit 12 – CKERR Checksum Check Error Interrupt Disable

Bit 11 – EORF End Of Refresh Interrupt Disable

Bit 10 – EOH End Of Hide Interrupt Disable

Bit 9 – EOF End Of Flush Interrupt Disable

Bit 8 – EOR End Of Read Interrupt Disable

Bit 7 – WERR Write Error Interrupt Disable

Bit 6 – IVERR Invalidation Error Interrupt Disable

Bit 5 – LKERR Locking Error Interrupt Disable

Bit 4 – PGERR Programming Error Interrupt Disable

Bit 3 – EOKT End Of Key Transfer Interrupt Disable

Bit 2 – EOI End Of Invalidation Interrupt Disable

Bit 1 – EOL End Of Locking Interrupt Disable

Bit 0 – EOP End Of Programming Interrupt Disable