38.6.2.6 DMA Address Alignment Requirements

When programming the DSCR.CHXADDR field of the DSCR structure, the following requirement must be met.

Table 38-3. DMA Address Alignment when CLUT Mode is Selected
CLUT ModeDMA Address Alignment
1 bpp8 bits
2 bpp8 bits
4 bpp8 bits
8 bpp8 bits
Table 38-4. DMA Address Alignment when RGB Mode is Selected
RGB ModeDMA Address Alignment
12 bpp RGB 44416 bits
16 bpp ARGB 444416 bits
16 bpp RGBA 444416 bits
16 bpp RGB 56516 bits
16 bpp TRGB 155516 bits
18 bpp RGB 66632 bits
18 bpp RGB 666 PACKED8 bits
19 bpp TRGB 166632 bits
19 bpp TRGB 16668 bits
24 bpp RGB 88832 bits
24 bpp RGB 888 PACKED8 bits
25 bpp TRGB 188832 bits
32 bpp ARGB 888832 bits
32 bpp RGBA 888832 bits
Table 38-5. DMA Address Alignment when YUV Mode is Selected
YUV ModeDMA Address Alignment
32 bpp AYCrCb32 bits
16 bpp YCrCb 4:2:232 bits
16 bpp semiplanar YCrCb 4:2:2Y 8 bits
CrCb 16 bits
16 bpp planar YCrCb 4:2:2Y 8 bits
Cr 8 bits
Cb 8 bits
12 bpp YCrCb 4:2:0Y 8 bits
CrCb 16 bits
12 bpp YCrCb 4:2:0Y 8 bits
Cr 8 bits
Cb 8 bits