24.3.1 EBI Chip Select Register
| Name: | SFR_CCFG_EBICSA |
| Offset: | 0x04 |
| Reset: | 0x00000300 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| DDR_MP_EN | NFD0_ON_D16 | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| DQIEN_F | EBI_DRIVE | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| EBI_DBPDC | EBI_DBPUC | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 1 | 1 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| EBI_CS5A | EBI_CS4A | EBI_CS3A | EBI_CS1A | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 |
Bit 25 – DDR_MP_EN DDR Multi-port Enable
| Value | Description |
|---|---|
| 0 | DDR Multi-port is disabled (default). |
| 1 | DDR Multi-port is enabled, performance is increased. |
Bit 24 – NFD0_ON_D16 NAND Flash Databus Selection
| Value | Description |
|---|---|
| 0 | NAND Flash I/Os are connected to D0–D7 (default). |
| 1 | NAND Flash I/Os are connected to D16–D23. |
Bit 20 – DQIEN_F Force Analog Input Comparator Configuration
| Value | Description |
|---|---|
| 0 | No effect |
| 1 | Enables the input comparator in the VDDIOM I/O data lines. This bit must be set to one in an initialization phase whenever an MPDDRC external component (DDR2 or LPDDR) and an SMC external component (e.g., NAND Flash) are multiplexed on the D0-D15 bus. |
Bit 16 – EBI_DRIVE EBI I/O Drive Configuration
| Value | Description |
|---|---|
| 0 | EBI D0–D15 Low Drive |
| 1 | EBI D0–D15 High Drive |
Bit 9 – EBI_DBPDC EBI Data Bus Pulldown Configuration
| Value | Description |
|---|---|
| 0 | EBI D0–D15 Data Bus bits are not internally pulled down. |
| 1 | EBI D0–D15 Data Bus bits are internally pulled down to the ground. |
Bit 8 – EBI_DBPUC EBI Data Bus Pullup Configuration
| Value | Description |
|---|---|
| 0 | EBI D0–D15 Data Bus bits are internally pulled up to the VDDIOM power supply. |
| 1 | EBI D0–D15 Data Bus bits are not internally pulled up. |
Bit 5 – EBI_CS5A EBI Chip Select 5 Assignment
| Value | Description |
|---|---|
| 0 | EBI Chip Select 5 is only assigned to the Static Memory Controller and EBI_NCS5 behaves as defined by the SMC. |
| 1 | EBI Chip Select 5 is assigned to the Static Memory Controller. |
Bit 4 – EBI_CS4A EBI Chip Select 4 Assignment
| Value | Description |
|---|---|
| 0 | EBI Chip Select 4 is only assigned to the Static Memory Controller and EBI_NCS4 behaves as defined by the SMC. |
| 1 | EBI Chip Select 4 is assigned to the Static Memory Controller. |
Bit 3 – EBI_CS3A EBI Chip Select 3 Assignment
| Value | Description |
|---|---|
| 0 | EBI Chip Select 3 is only assigned to the Static Memory Controller and EBI_NCS3 behaves as defined by the SMC. |
| 1 | EBI Chip Select 3 is assigned to the Static Memory Controller and the NAND Flash Logic is activated. |
Bit 1 – EBI_CS1A EBI Chip Select 1 Assignment
| Value | Description |
|---|---|
| 0 | EBI Chip Select 1 is assigned to the Static Memory Controller (SMC). |
| 1 | EBI Chip Select 1 is assigned to the MPDDRC or the SDRAMC controller. |