Figure 49-99. Falling Edge
Response Time vs. VDD (VCM =
VDD/2, SP[1:0] = 0x0)
|
Figure 49-100. Falling Edge
Response Time vs. VDD (VCM =
VDD/2, SP[1:0] = 0x1)
|
Figure 49-101. Falling Edge
Response Time vs. VDD (VCM =
VDD/2, SP[1:0] = 0x2)
|
Figure 49-102. Falling Edge
Response Time vs. VDD (VCM =
VDD/2, SP[1:0] = 0x3)
|
Figure 49-103. Rising Edge
Response Time vs. VDD (VCM =
VDD/2, SP[1:0] = 0x0)
|
Figure 49-104. Rising Edge
Response Time vs. VDD (VCM =
VDD/2, SP[1:0] = 0x1)
|
Figure 49-105. Rising Edge
Response Time vs. VDD (VCM =
VDD/2, SP[1:0] = 0x2)
|
Figure 49-106. Rising Edge
Response Time vs. VDD (VCM =
VDD/2, SP[1:0] = 0x3)
|
Figure 49-107. Input Offset
vs. Common Mode Voltage (VDD = 2.0V)
|
Figure 49-108. Input
Hysteresis vs. Common Mode Voltage (VDD =
2.0V)
|
Figure 49-109. Input Offset
vs. Common Mode Voltage (VDD = 3.0V)
|
Figure 49-110. Input
Hysteresis vs. Common Mode Voltage (VDD =
3.0V)
|
Figure 49-111. Input Offset
vs. Common Mode Voltage (VDD = 5.5V)
|
Figure 49-112. Input
Hysteresis vs. Common Mode Voltage (VDD =
5.5V)
|
