14.3.2.3 Event Generators
Each event channel has several possible event generators, but only one can be selected at a time. The event generator for a channel is selected by writing to the respective Channel n Generator Selection (EVSYS.CHANNELn) register. By default, the channels are not connected to any event generator. For details on event generation, refer to the documentation of the corresponding peripheral.
A generated event is either synchronous or asynchronous to the device peripheral clock (CLK_PER). Asynchronous events can be generated outside the normal edges of the peripheral clock, making the system respond faster than the selected clock frequency would suggest. Asynchronous events can also be generated while the device is in a Sleep mode when the peripheral clock is not running.
Any generated event is classified as either a pulse event or a level event. In both cases, the event can be either synchronous or asynchronous, with properties according to the table below.
| Event Type | Sync/Async | Description |
|---|---|---|
| Pulse | Sync | An event generated from CLK_PER that lasts one clock cycle |
| Async | An event generated from a clock other than CLK_PER lasting one clock cycle | |
| Level | Sync | An event generated from CLK_PER that lasts multiple clock cycles |
| Async | An event generated without a clock (for example, a pin or a comparator), or an event generated from a clock, other than CLK_PER that lasts multiple clock cycles |
The properties of both the generated event and the intended event user must be considered to ensure reliable and predictable operation.
The table below shows the available event generators for this device family.
| Generator | Event | Generating Clock Domain | Length of Event | Constraints for Synchronous User |
|---|---|---|---|---|
| UPDI | SYNC character | CLK_PDI | Waveform: SYNC char on PDI RX input synchronized to CLK_PDI | Synchronizing clock in user must be fast enough to ensure that the event is seen by the user |
| RTC | Overflow | CLK_RTC | Pulse: 1 * CLK_RTC | None |
| Compare Match | CLK_RTC | Pulse: 1 * CLK_RTC | ||
| PIT | RTC Prescaled clock | CLK_RTC | Level | |
| CCL-LUT | LUT output | Asynchronous | Depends on CCL configuration | The clock source used for CCL must be slower or equal to CLK_PER or input signals to CCL are stable for at least Tclk_per |
| AC | Comparator result | Asynchronous | Level: Typically ≥1 us | The frequency of input signals to AC must be ≤fclk_per to ensure that the event is seen by the synchronous user |
| ADC | Result ready | CLK_ADC | Pulse: 1 * CLK_PER | None |
| PORT | Pin input | Asynchronous | Level: Externally controlled | The input signal must be stable for longer than fclk_per |
| USART | USART Baud clock | TXCLK | Level | None |
| SPI | SPI Host clock | SCK | Level | None |
| TCA | Overflow | CLK_PER | Pulse: 1 * CLK_PER | None |
| Underflow in split mode | CLK_PER | Pulse: 1 * CLK_PER | ||
| Compare match ch 0 | CLK_PER | Pulse: 1 * CLK_PER | ||
| Compare match ch 1 | CLK_PER | Pulse: 1 * CLK_PER | ||
| Compare match ch 2 | CLK_PER | Pulse: 1 * CLK_PER | ||
| TCB | CAPT interrupt flag set | CLK_PER | Pulse: 1 * CLK_PER | None |