14.5.2 Channel n Generator Selection

Each channel can be connected to one event generator. Not all generators can be connected to all channels. Refer to the table below to see which generator sources can be routed onto each channel and the generator value to be written to EVSYS.CHANNELn to achieve this routing. Writing the value 0x00 to EVSYS.CHANNELn turns the channel off.

Name:	CHANNEL
Offset:	0x10 + n*0x01 [n=0..7]
Reset:	0x00
Property:	-


Bit	7	6	5	4	3	2	1	0
	GENERATOR[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 7:0 – GENERATOR[7:0] Channel Generator Selection


GENERATOR		INPUT	Async/Sync	CH0	CH1	CH2	CH3	CH4	CH5	CH6	CH7
binary	hex	INPUT	Async/Sync	CH0	CH1	CH2	CH3	CH4	CH5	CH6	CH7
0000_0001	0x01	UPDI	Sync	UPDI
0000_0110	0x06	RTC_OVF	Async	OVF
0000_0111	0x07	RTC_CMP	Async	CMP
0000_1000	0x08	RTC_PIT0	Async	DIV8192	DIV512	DIV8192	DIV512	DIV8192	DIV512	DIV8192	DIV512
0000_1001	0x09	RTC_PIT1	Async	DIV4096	DIV256	DIV4096	DIV256	DIV4096	DIV256	DIV4096	DIV256
0000_1010	0x0A	RTC_PIT2	Async	DIV2048	DIV128	DIV2048	DIV128	DIV2048	DIV128	DIV2048	DIV128
0000_1011	0x0B	RTC_PIT3	Async	DIV1024	DIV64	DIV1024	DIV64	DIV1024	DIV64	DIV1024	DIV64
0001_00nn	0x10-0x13	CCL_LUTn	Async	LUTn
0010_0000	0x20	AC0	Async	OUT
0010_0100	0x24	ADC0	Sync	RESRDY
0100_0nnn	0x40-0x47	PORT0_PINn	Async	PORTA_PINn		PORTC_PINn		PORTE_PINn
0100_1nnn	0x48-0x4F	PORT1_PINn	Async	PORTB_PINn		PORTD_PINn		PORTF_PINn
0110_0nnn	0x60-0x67	USARTn	Sync	XCK
0110_1000	0x68	SPI0	Sync	SCK
1000_0000	0x80	TCA0_OVF_LUNF	Sync	OVF/LUNF
1000_0001	0x81	TCA0_HUNF	Sync	HUNF
1000_0100	0x84	TCA0_CMP0	Sync	CMP0
1000_0101	0x85	TCA0_CMP1	Sync	CMP1
1000_0110	0x86	TCA0_CMP2	Sync	CMP2
1010_nnn0	0xA0-0xAE	TCBn	Sync	CAPT

ATmega4808/4809

14.5.2 Channel n Generator Selection

Bits 7:0 – GENERATOR[7:0] Channel Generator Selection