27.5.7 LUT n Control B
Note:
- SPI connections to the CCL work in Host SPI mode only.
- USART connections to the CCL work only when the USART is in one of the following
modes:
- Asynchronous USART
- Synchronous USART host
| Name: | LUTnCTRLB |
| Offset: | 0x09 + n*0x04 [n=0..3] |
| Reset: | 0x00 |
| Property: | Enable-Protected |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| INSEL1[3:0] | INSEL0[3:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 7:4 – INSEL1[3:0] LUT n Input 1 Source Selection
These bits select the source for input 1 of LUT n.
| Value | Name | Description |
|---|---|---|
0x0 | MASK | None (masked) |
0x1 | FEEDBACK | Feedback input |
0x2 | LINK | Output from LUTn+1 |
0x3 | EVENTA | Event input source A |
0x4 | EVENTB | Event input source B |
0x5 | IO | I/O-pin LUTn-IN1 |
0x6 | AC0 | AC0 out |
0x7 | - | Reserved |
0x8 | USART1 | USART1 TXD |
0x9 | SPI0 | SPI0 MOSI |
0xA | TCA0 | TCA0 WO1 |
0xB | - | Reserved |
0xC | TCB1 | TCB1 WO |
Other | - | Reserved |
Bits 3:0 – INSEL0[3:0] LUT n Input 0 Source Selection
These bits select the source for input 0 of LUT n.
| Value | Name | Description |
|---|---|---|
0x0 | MASK | None (masked) |
0x1 | FEEDBACK | Feedback input |
0x2 | LINK | Output from LUTn+1 |
0x3 | EVENTA | Event input source A |
0x4 | EVENTB | Event input source B |
0x5 | IO | I/O-pin LUTn-IN0 |
0x6 | AC0 | AC0 out |
0x7 | - | Reserved |
0x8 | USART0 | USART0 TXD |
0x9 | SPI0 | SPI0 MOSI |
0xA | TCA0 | TCA0 WO0 |
0xB | - | Reserved |
0xC | TCB0 | TCB0 WO |
Other | - | Reserved |