3.6.5.5.4 Quality Of Service Arbitration

This arbitration scheme is enabled when the ARB field is set to 3 (see MPDDRC Configuration Arbiter Register).

The arbitration scheme is organized in priority pools corresponding each to an access criticality class as shown in the corresponding Latency Quality of Service column in the following table. When the Latency Quality of Service is enabled for a host-client pair through the system bus matrix (refer to the section "Bus Matrix (MATRIX)"), the priority pool number to use for arbitration at the client port is determined from the host. When the Latency Quality of Service is disabled, it is determined through the system bus matrix user interface. Refer to “MATRIX Priority Register A For Clients” in the section "Bus Matrix (MATRIX)".

Round-robin priority is used in the highest and lowest priority pools 3 and 0, whereas fixed level priority is used between priority pools and in the intermediate priority pools 2 and 1.

For each client, each host is assigned to one of the client priority pools based on the Latency Quality of Service inputs or to the priority registers for clients (MxPR fields of MATRIX_PRAS and MATRIX_PRBS, refer to the section "Bus Matrix (MATRIX)"). When evaluating host requests, this priority pool level always takes precedence.

After reset, most of the hosts belong to the lowest priority pool (MxPR = 0, Background Transfer) and are therefore granted bus access in a true round-robin order.

The highest priority pool must be specifically reserved for hosts requiring very low access latency. If more than one host belong to this pool, those hosts are granted bus access in a biased round-robin manner which enables tight and deterministic maximum access latency from system bus requests. In the worst case, any currently occurring high-priority host request is granted after the current bus host access has ended and any other high priority pool host requests have been granted once each.

The lowest priority pool shares the remaining bus bandwidth between system bus hosts.

Intermediate priority pools enable fine priority tuning. Typically, a latency-sensitive host or a bandwidth-sensitive host uses such a priority level. The higher the priority level (MxPR value, refer to the section "Bus Matrix (MATRIX)"), the higher the host priority.

All combinations of MxPR values are allowed for all hosts and clients. For example, some hosts might be assigned the highest priority pool (round-robin), and remaining hosts the lowest priority pool (round-robin), with no host for intermediate fixed priority levels.

Some hosts, such as LCD or DMA, drive a signal named HNBREQ on the system bus to indicate the number of transfers to be performed. When the field MPDDRC_CONF_ARBITER.KEEP_LAYER is set to 1, the host with the highest LQOS value and a HNBREQ value different from 0 continues to be granted, even during a last data phase with IDLE cycles.