6.3.7.3 I2SMCC Mode Register B
This register can only be written if WPCFEN is cleared in the Inter-IC Sound Write Protection Mode Register.
The I2SMCC_MRB must only be written when the I2SMCC is stopped in order to avoid unexpected behavior on the I2SMCC_WS, I2SMCC_CK and I2SMCC_DOUT outputs. The proper sequence is to write to I2SMCC_MRB, then write to I2SMCC_CR to enable the I2SMCC or to disable the I2SMCC before writing a new value to I2SMCC_MRB.
| Name: | I2SMCC_MRB |
| Offset: | 0x08 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| DMACHUNK[1:0] | |||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 | |||||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Access | |||||||||
| Reset |
Bits 9:8 – DMACHUNK[1:0] DMA Chunk Size
| Value | Name | Description |
|---|---|---|
| 0 | 1_WORD | A DMA transfer request is issued when at least 1 word is empty in the FIFO. |
| 1 | 2_WORDS | A DMA transfer request is issued when at least 2 words are empty in the FIFO. |
| 2 | 4_WORDS | A DMA
transfer request is issued when at least 4 words are empty in the FIFO.
Limitations exist when operating in Mono or TDM. See TX DMA Chunk Configurations and RX DMA Chunk Configurations. |
| 3 | 8_WORDS | A DMA
transfer request is issued when at least 8 words are empty in the
FIFO. Limitations exist when operating in Mono or TDM. See TX DMA Chunk Configurations and RX DMA Chunk Configurations. |