6.3.7.8 I2SMCC Interrupt Status Register A
| Name: | I2SMCC_ISRA |
| Offset: | 0x1C |
| Reset: | 0x00000003 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| RXROVF3 | RXLOVF3 | RXROVF2 | RXLOVF2 | RXROVF1 | RXLOVF1 | RXROVF0 | RXLOVF0 | ||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| RXRRDY3 | RXLRDY3 | RXRRDY2 | RXLRDY2 | RXRRDY1 | RXLRDY1 | RXRRDY0 | RXLRDY0 | ||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| TXRUNF3 | TXLUNF3 | TXRUNF2 | TXLUNF2 | TXRUNF1 | TXLUNF1 | TXRUNF0 | TXLUNF0 | ||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TXRRDY3 | TXLRDY3 | TXRRDY2 | TXLRDY2 | TXRRDY1 | TXLRDY1 | TXRRDY0 | TXLRDY0 | ||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
Bits 25, 27, 29, 31 – RXROVFx I2S Receive Right x (x=0 only) or TDM Channel [2x]+1 Overrun Flag (Cleared on read)
| Value | Description |
|---|---|
| 0 | Cleared when I2SMCC_ISRA is read. |
| 1 | Set when an overrun error occurs in I2SMCC_RHR. |
Bits 24, 26, 28, 30 – RXLOVFx I2S Receive Left x (x=0 only) or TDM Channel 2x Overrun Flag (Cleared on read)
| Value | Description |
|---|---|
| 0 | Cleared when I2SMCC_ISRA is read. |
| 1 | Set when an overrun error occurs in I2SMCC_RHR. |
Bits 17, 19, 21, 23 – RXRRDYx I2S Receive Right x (x=0 only) or TDM Channel [2x]+1 Ready Flag (Cleared by reading I2SMCC_RHR)
| Value | Description |
|---|---|
| 0 | Cleared when a predefined number of read accesses are performed in I2SMCC_RHR. The predefined number depends on the configuration of I2SMCC_MRA.WIRECFG / FORMAT and varies from 1 to 8. |
| 1 | Set when received data is available in I2SMCC_RHR. |
Bits 16, 18, 20, 22 – RXLRDYx I2S Receive Left x (x=0 only) or TDM Channel 2x Ready Flag (Cleared by reading I2SMCC_RHR)
| Value | Description |
|---|---|
| 0 |
Cleared when a predefined number of read accesses is performed in I2SMCC_RHR. The predefined number depends on the configuration of I2SMCC_MRA.WIRECFG/FORMAT and varies from 1 to 7. |
| 1 |
Set when received data is available in I2SMCC_RHR. |
Bits 9, 11, 13, 15 – TXRUNFx I2S Transmit Right x (x=0 only) or TDM Channel [2x]+1 Underrun Flag (Cleared on read)
| Value | Description |
|---|---|
| 0 | Cleared when the I2SMCC_ISRA is read. |
| 1 | Set when an underrun error occurs in I2SMCC_THR. |
Bits 8, 10, 12, 14 – TXLUNFx I2S Transmit Left x (x=0 only) or TDM Channel 2x Underrun (Cleared on read)
| Value | Description |
|---|---|
| 0 | Cleared when I2SMCC_ISRA is read. |
| 1 | Set when an underrun error occurs in I2SMCC_THR. |
Bits 1, 3, 5, 7 – TXRRDYx I2S Transmit Right x (x=0 only) or TDM Channel [2x]+1 Ready Flag (Cleared by writing I2SMCC_THR)
| Value | Description |
|---|---|
| 0 |
Cleared when a predefined number of write accesses is performed in I2SMCC_THR. The predefined number depends on the configuration of I2SMCC_MRA.WIRECFG/FORMAT and varies from 1 to 8. |
| 1 |
Set when I2SMCC_THR is empty. |
Bits 0, 2, 4, 6 – TXLRDYx I2S Transmit Left x (x=0 only) or TDM Channel 2x Ready Flag (Cleared by writing I2SMCC_THR)
| Value | Description |
|---|---|
| 0 | Cleared when a predefined number of write accesses is performed in I2SMCC_THR. The predefined number depends on the configuration of I2SMCC_MRA.WIRECFG/FORMAT and varies from 1 to 7. |
| 1 | Set when I2SMCC_THR is empty. |