5.7.6.31 CSI2DC GLP Interrupt Status Register
| Name: | CSI2DC_GLPISR |
| Offset: | 0x88 |
| Reset: | 0x00000000 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| RE[3:0] | EB[3:0] | ||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| BL[3:0] | NU[3:0] | ||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 15:12 – RE[3:0] Reserved Generic Long Packet Ready Interrupt Status Bit
| Value | Description |
|---|---|
| 0 | A bit cleared at position i in the field BL indicates that no reserved packet interrupt is pending for virtual channel i. |
| 1 | A bit set at position i in the field BL indicates that a reserved packet interrupt is pending for virtual channel i. This bit is reset after the register read operation. |
Bits 11:8 – EB[3:0] Embedded 8-bit data Generic Long Packet Ready Interrupt Status Bit
| Value | Description |
|---|---|
| 0 | A bit cleared at position i in the field EB indicates that no embedded data packet interrupt is pending for virtual channel i. |
| 1 | A bit set at position i in the field EB indicates that an embedded data packet interrupt is pending for virtual channel i. This bit is reset after the register read operation. |
Bits 7:4 – BL[3:0] Blanking Data Generic Long Packet Ready Interrupt Status Bit
| Value | Description |
|---|---|
| 0 | A bit cleared at position i in the field BL indicates that no blanking data packet interrupt is pending for virtual channel i. |
| 1 | A bit set at position i in the field BL indicates that a blanking packet interrupt is pending for virtual channel i. This bit is reset after the register read operation. |
Bits 3:0 – NU[3:0] Null Generic Long Packet Ready Interrupt Status Bit
| Value | Description |
|---|---|
| 0 | A bit cleared at position i in the field NU indicates that no null packet interrupt is pending for virtual channel i. |
| 1 | A bit set at position i in the field NU indicates that a null packet interrupt is pending for virtual channel i. This bit is reset after the register read operation. |