5.7.6.44 CSI2DC Data Pipe Interrupt Status Register

Name: CSI2DC_DPISR
Offset: 0xD4
Reset: 0x00000000
Property: Read-only

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
 LTESTEDATOVFRXOVF1RXOVF0RXRDY1RXRDY0CAPTURE 
Access RRRRRRRR 
Reset 00000000 

Bit 7 – LTE Packet Longer Than Expected

ValueDescription
0

No LTE packet detected.

1

A packet has been received but the actual length is longer that the packet word count value.

Bit 6 – STE Packet Shorter Than Expected

ValueDescription
0

No STE packet detected since the last clear operation of the register.

1

A packet has been received but the actual length is shorter that the packet word count value.

Bit 5 – DATOVF Data Overflow

ValueDescription
0

No overflow detected since the last clear operation of the register.

1

Data overflow in the clock domain crossing FIFO.

Bit 4 – RXOVF1 Bank 1 Overflow

ValueDescription
0

No overflow detected since the last clear operation of the register.

1

An overflow occurred in bank 1.

Bit 3 – RXOVF0 Bank 0 Overflow

ValueDescription
0

No overflow detected since the last clear operation of the register.

1

An overflow occurred in bank 0.

Bit 2 – RXRDY1 Bank 1 Packet Received

ValueDescription
0

No packet received in bank 1 since the last clear operation of the register.

1

A new packet has been captured in the data pipe.

Bit 1 – RXRDY0 Bank 0 Packet Received

ValueDescription
0

No packet received in bank 0 since the last clear operation of the register.

1

A new packet has been captured in the data pipe.

Bit 0 – CAPTURE Captured Frame

ValueDescription
0

No frame captured on the data pipe interface since the last clear operation of the register.

1

A new frame has been captured in the data pipe.